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參數(shù)資料
| 型號： | 954204AGT |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘產(chǎn)生/分配 |
| 英文描述： | 400 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56 |
| 封裝： | 6.10 MM, 0.50 MM PITCH, MO-153, TSSOP-56 |
| 文件頁數(shù)： | 5/20頁 |
| 文件大小： | 261K |
| 代理商： | 954204AGT |
13
Integrated
Circuit
Systems, Inc.
ICS954204
0933D—03/16/05
SMBus Table: Vendor & Revision ID Register
Pin #
Nam e
Control Function
Type
0
1
PWD
Bit 7
RID3
R
-
x
Bit 6
RID2
R
-
x
Bit 5
RID1
R
-
x
Bit 4
RID0
R
-
x
Bit 3
VID3
R
-
0
Bit 2
VID2
R
-
0
Bit 1
VID1
R
-
0
Bit 0
VID0
R
-
1
SMBus Table: Clock Request Control Register
Pin #
Nam e
Control
Type
0
1
PWD
Bit 7
-
Bit 6
CLKREQ B# Control
SRCCLK5 is controlled
RW
Not Controlled
Controlled
1
Bit 5
CLKREQ B# Control
SRCCLK3 is c ontrolled
RW
Not Controlled
Controlled
0
Bit 4
CLKREQ B# Control
SRCCLK1 is c ontrolled
RW
Not Controlled
Controlled
0
Bit 3
-
Bit 2
CLKREQ A# Control
SRCCLK4 is controlled
RW
Not Controlled
Controlled
1
Bit 1
CLKREQ A# Control
SRCCLK2 is c ontrolled
RW
Not Controlled
Controlled
0
Bit 0
CLKREQ A# Control
SRCCLK0 is c ontrolled
RW
Not Controlled
Controlled
0
SMBus Table: LCDCLK_SS Control Register
Pin #
Nam e
Control
Type
0
1
PWD
Bit 7
LCDCLK_SS3
Bit S3
RW
0
Bit 6
LCDCLK_SS2
Bit S2
RW
1
Bit 5
LCDCLK_SS1
Bit S1
RW
1
Bit 4
LCDCLK_SS0
Bit S0
RW
1
Bit 3
*SEL SRC_LCDCLK#
Select
LCDCLK_SS/SRCCLK0
R
LCDCLK
SRCCLK0
-
Bit 2
LCDCLK_SS/SRCCLK0
Enable
O utput Enable
RW
Dis able (HiZ)
Enable
1
Bit 1
LCDCLK_SS Spread
Enable
Enable SS
RW
O FF
O N
1
Bit 0
0
Res erv ed
REVISIO N ID
33
-
Byte 8
-
VENDO R ID
-
32
-
Byte 7
-
Byte 9
See LCDCLK_SS Frequenc y
Selec t Table 2
17,18
Res erv ed
9
17, 18
-
Byte9/
bit1
S3
S2
S1
S0
Pin 17/18
MHz
Spread % Spread Type
0
X
100.00
-
1000
0
100.00
0.8
Down
1000
1
100.00
1
Down
1001
0
100.00
1.25
Down
1001
1
100.00
1.5
Down
1010
0
100.00
1.75
Down
1010
1
100.00
2
Down
1011
0
100.00
2.5
Down
1011
1
100.00
3
Down
1100
0
100.00
+/-0.3
Center
1100
1
100.00
+/-0.4
Center
1101
0
100.00
+/-0.5
Center
1101
1
100.00
+/-0.6
Center
1110
0
100.00
+/-0.8
Center
1110
1
100.00
+/-1.0
Center
1111
0
100.00
+/-1.25
Center
1111
1
100.00
+/-1.5
Center
Table 2: LCDCLK_SS Frequency Select
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PDF描述 |
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| 954206BGT | 400 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56 |
| 954206BFT | 400 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56 |
| 954206BFLFT | 400 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56 |
| 9552-6006-01 | RF/MICROWAVE FIXED ATTENUATOR |
| 9552-6006-03 | RF/MICROWAVE FIXED ATTENUATOR |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 954204BGLF | 制造商:Integrated Device Technology Inc 功能描述:56 TSSOP (LEAD FREE) - Rail/Tube |
| 954204BGLN | 制造商:Integrated Device Technology Inc 功能描述:PLL Clock Synthesizer Dual 56-Pin TSSOP Tube |
| 954204BGLNT | 制造商:Integrated Device Technology Inc 功能描述:PLL Clock Synthesizer Dual 56-Pin TSSOP T/R |
| 954204CGLF | 功能描述:時鐘合成器/抖動清除器 RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| 954204CGLFT | 功能描述:時鐘合成器/抖動清除器 RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
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