參數(shù)資料
型號(hào)： 954204AGT
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： 時(shí)鐘產(chǎn)生/分配
英文描述： 400 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56
封裝： 6.10 MM, 0.50 MM PITCH, MO-153, TSSOP-56
文件頁(yè)數(shù)： 6/20頁(yè)
文件大小： 261K
代理商： 954204AGT
14
Integrated
Circuit
Systems, Inc.
ICS954204
0933D—03/16/05
CLKREQ# - Assertion (transition from logic “1” to logic “0”)
The impact of asserting the CLKREQ# pin is that the SRCCLK output will become active per the timing found in
Table 4. The clock will become active in a glitch free manner, providing a full cycle at the time it becomes active.
CLKREQ# - De-Assertion (transition from logic “0” to logic “1”)
The impact of asserting the CLKREQ# pin is that the SRCCLK output will become inactive setliing in the Tristate
condition per the timing found in Table 4. The clock will become inactive in a glitch free manner.
Power Stable to Device
TSRCSTBL
TPVCRL
VPCIEXDEV
SRCCLK
CLKREQ#
Figure 1. Power-Up CLKREQ# Timing
CLKREQ#
SRCCLK
Figure 2. CLKREQ# Control Timing
Symbol
Parameter
Min
Max
Units
TPVCRL
Power Valid to CLKREQ# Output Active
(Fig. 1)
100
s
TSRCSTBL
SRC Clock Stablilzation Time from assertion
of CLKREQ# (Fig. 1)
800
s
1This timing is valid only after system clocks are stable.
Table 3. Power-Up CLKREQ# Timing
1
Symbol
Parameter
Min
Max
Units
TCRHoff
CLKREQ# De-asserted High to SRCCLK
Parked (Fig. 2)
0
s
TCRHon
CLKREQ# Asserted LOW to SRCCLK
Active (Fig. 2)
0.4
s
Table 4. CLKREQ# Control Timing
相關(guān)PDF資料
PDF描述
954206BGT 400 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56
954206BFT 400 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56
954206BFLFT 400 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56
9552-6006-01 RF/MICROWAVE FIXED ATTENUATOR
9552-6006-03 RF/MICROWAVE FIXED ATTENUATOR
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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