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參數(shù)資料
| 型號： | 954206BGT |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時(shí)鐘產(chǎn)生/分配 |
| 英文描述： | 400 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56 |
| 封裝： | 6.10 MM, 0.50 MM PITCH, MO-153N, TSSOP-56 |
| 文件頁數(shù)： | 12/20頁 |
| 文件大?。?/td> | 315K |
| 代理商： | 954206BGT |
2
Integrated
Circuit
Systems, Inc.
ICS954206B
Advance Information
0940—06/23/05
Pin Description
PIN #
PIN NAME
TYPE
DESCRIPTION
1
VDDPCI
PWR
Power supply for PCI clocks, nominal 3.3V
2
GND
PWR
Ground pin.
3
PCICLK3
OUT
PCI clock output.
4
PCICLK4
OUT
PCI clock output.
5
PCICLK5
OUT
PCI clock output.
6
GND
PWR
Ground pin.
7
VDDPCI
PWR
Power supply for PCI clocks, nominal 3.3V
8
ITP_EN/PCICLK_F0
I/O
Free running PCI clock not affected by PCI_STOP# through I2C .
ITP_EN: latched input to select pin functionality
1 = CPU_2_ITP pair
0 = PCIEX_6 pair
9
*SELPCIEX_LCDCLK#/PCI
CLK_F1
I/O
Latched select input for LCDCLK/PCIEX output 0 = LCDCLK, 1 = PCIEX /
Free running 3.3V PCI clock output.
10
Vtt_PwrGd#/PD
IN
Vtt_PwrGd# is an active low input used to determine when latched inputs
are ready to be sampled. PD is an asynchronous active high input pin used
to put the device into a low power state. The internal clocks, PLLs and the
crystal oscillator are stopped.
11
VDD48
PWR
Power pin for the 48MHz output.3.3V
12
FSLA/USB_48MHz
I/O
3.3V tolerant input for CPU frequency selection. Refer to input electrical
characteristics for Vil_FS and Vih_FS values. / Fixed 48MHz USB clock
output. 3.3V.
13
GND
PWR
Ground pin.
14
DOTT_96MHz
OUT
True clock of differential pair for 96.00MHz DOT clock.
15
DOTC_96MHz
OUT
Complement clock of differential pair for 96.00MHz DOT clock.
16
FSLB/TEST_MODE
IN
3.3V tolerant input for CPU frequency selection. Refer to input electrical
characteristics for Vil_FS and Vih_FS values. TEST_MODE is a real time
input to select between Hi-Z and REF/N divider mode while in test mode.
Refer to Test Clarification Table.
17
LCDCLK_SS/PCIEX0T
OUT
True clock of LCDCLK_SS output / True clock of PCI Express differential
pair. Selected by SELPCIEX_LCDCLK#
18
LCDCLK_SS/PCIEX0C
OUT
Complementary clock of LCDCLK_SS output / Complementary clock of PCI
Express differential pair. Selected by SELPCIEX_LCDCLK#
19
PCIEXT1
OUT
True clock of differential PCI_Express pair.
20
PCIEXC1
OUT
Complement clock of differential PCI_Express pair.
21
VDDPCIEX
PWR
Power supply for PCI Express clocks, nominal 3.3V
22
PCIEXT2
OUT
True clock of differential PCI_Express pair.
23
PCIEXC2
OUT
Complement clock of differential PCI_Express pair.
24
PCIEXT3
OUT
True clock of differential PCI_Express pair.
25
PCIEXC3
OUT
Complement clock of differential PCI_Express pair.
26
SATACLKT
OUT
True clock of differential SATA pair.
27
SATACLKC
OUT
Complement clock of differential SATA pair.
28
VDDPCIEX
PWR
Power supply for PCI Express clocks, nominal 3.3V
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