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參數(shù)資料
| 型號(hào)： | 954206BGT |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類(lèi)： | 時(shí)鐘產(chǎn)生/分配 |
| 英文描述： | 400 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56 |
| 封裝： | 6.10 MM, 0.50 MM PITCH, MO-153N, TSSOP-56 |
| 文件頁(yè)數(shù)： | 9/20頁(yè) |
| 文件大?。?/td> | 315K |
| 代理商： | 954206BGT |
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17
Integrated
Circuit
Systems, Inc.
ICS954206B
Advance Information
0940—06/23/05
I
2C Table: PLL2 Spread Spectrum Control Register
Control
Function
Bit 7
Reserved
R
0
Bit 6
SSP14
RW
X
Bit 5
SSP13
RW
X
Bit 4
SSP12
RW
X
Bit 3
SSP11
RW
X
Bit 2
SSP10
RW
X
Bit 1
SSP9
RW
X
Bit 0
SSP8
RW
X
Byte 20
Pin #
Name
-
Spread Spectrum
Programming b(14:8)
PWD
Type
1
--
0
These Spread Spectrum bits in Byte 19
and 20 will program the spread
pecentage. It is recommended to use
ICS Spread % table for spread
programming.
-
Test Clarification Table
Comments
FSLC/TES
T_SEL
HW PIN
FSLB/TES
T_MODE
HW PIN
TEST
ENTRY
BIT
W1b7
REF/N or
HI-Z
W2b3
OUTPUT
0X
0
X
NORMAL
10
X
0
HI-Z
10
X
1
REF/N
11
X
0
REF/N
11
X
1
REF/N
0X
1
0
HI-Z
0X
1
REF/N
W1b7: 1= ENTER TEST MODE, Default = 0 (NORMAL OPERATION)
W2b3: 1= REF/N, Default = 0 (HI-Z)
HW
SW
Power-up w/ TEST_SEL = 1 to enter test mode
Cycle power to disable test mode
FSLC./TEST_SEL -->3-level latched input
If power-up w/ V>2.0V (-0.3V) then use TEST_SEL
If power-up w/ V<2.0V (-0.3V) then use FSLC
FSLB/TEST_MODE -->low Vth input
TEST_MODE is a
If TEST_SEL HW pin is 0 during power-up,
test mode can be invoked through W1b7.
If test mode is invoked by W1b7, only W2b3
is used to select HI-Z or REF/N
FSLB/TEST_Mode pin is not used.
Cycle power to disable test mode, one shot control
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