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參數(shù)資料
| 型號(hào)： | 9601-01 |
| 廠商： | PEREGRINE SEMICONDUCTOR CORP |
| 元件分類： | PLL合成/DDS/VCOs |
| 英文描述： | 2200 MHz UltraCMOS⑩ Integer-N PLL for Rad Hard Applications |
| 中文描述： | PHASE LOCKED LOOP, CQCC44 |
| 封裝： | CERAMIC, QFJ-44 |
| 文件頁數(shù)： | 11/14頁 |
| 文件大?。?/td> | 257K |
| 代理商： | 9601-01 |
Product Specification
PE9601
Page 6 of 14
2005 Peregrine Semiconductor Corp. All rights reserved.
Document No. 70-0025-05
│ UltraCMOS RFIC Solutions
Table 5. DC Characteristics
VDD = 3.0 V, -40° C < TA < 85° C, unless otherwise specified
Symbol
Parameter
Test Program Name
Conditions
Min
Typ
Max
Units
IDD
Operational supply current;
Prescaler enabled 2 GHz
center frequency with 10
MHz reference input.
IDD_T_oper_at_2 GHz
VDD = 2.85 to 3.15 V
24
mA
Digital Inputs: All except fr, R0, Fin, Fin
VIH
High level input voltage
LEVELS_”xxx”_VIH(V)
where “xxx” is name of pin
being tested
VDD = 2.85 to 3.15 V
0.7 x VDD
V
VIL
Low level input voltage
LEVELS_”xxx”_VIL(V)
where “xxx” is name of pin
being tested
VDD = 2.85 to 3.15 V
0.3 x VDD
V
IIH
High level input current
(Pull-down resistor on
input)
IIH_”xxx”_(A) where “xxx”
is name of pin being
tested
VIH = VDD = 3.15 V
+100
A
IIL
Low level input current
IIL_”xxx”_(A) where “xxx”
is name of pin being
tested
VIL = 0, VDD = 3.15 V
-1
A
Reference Divider input: fr
IIHR
High level input current
IIH_FR_(A)
VIH = VDD = 3.15 V
+50
A
IILR
Low level input current
IIL_FR_(A)
VIL = 0, VDD = 3.15 V
-50
A
R0 Input (Pull-up Resistor): R0
IIHR
High level input current
(Pull-down resistor on
input)
IIH_R0_(A)
VIH = VDD = 3.15 V
+100
A
IILR
Low level input current
IIL_R0_(A)
VIL = 0, VDD = 3.15 V
-3
A
Counter and phase detector outputs: fc, fp.
VOLD
Output voltage LOW
LEVELS_”xxx”_VOL(V)
where “xxx” is name of pin
being tested
Iout = 6 mA
0.4
V
VOHD
Output voltage HIGH
LEVELS_”xxx”_VOH(V)
where “xxx” is name of pin
being tested
Iout = -3 mA
VDD - 0.4
V
Lock detect outputs: Cext, LD
VOLC
Output voltage LOW, Cext
LEVELS_CEXT_VOL(V)
Iout = 0.1 mA
0.4
V
VOHC
Output voltage HIGH, Cext
LEVELS_CEXT_VOH(V)
Iout = -0.1 mA
VDD - 0.4
V
VOLLD
Output voltage LOW, LD
LEVELS_ LD_VOL(V)
Iout = 6 mA
0.4
V
Charge Pump output: CP
ICP - Source
Drive current
CP_src_at_0.5 VDD (A)
VCP = VDD / 2
-2.6
-2
-1.4
mA
ICP – Sink
Drive current
CP_snk_at_0.5 VDD (A)
VCP = VDD / 2
1.4
2
2.6
mA
ICPL
Leakage current
CP_lkg_PD_DX (A)
1.0 V < VCP < VDD –
1.0 V
-1
1
A
ICP – Source
vs. ICP Sink
Sink vs. source mismatch
CP_srcvsnk_at_0.5 VDD
VCP = VDD / 2,
TA = 25° C
25
%
ICP vs. VCP
Output current magnitude
variation vs. voltage
CP_snk_var,
CP_src_var
1.0V < VCP < VDD –
1.0 V TA = 25° C
25
%
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