參數(shù)資料
型號： 9DB1200CGLF
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： 時鐘及定時
英文描述： 9DB SERIES, PLL BASED CLOCK DRIVER, 12 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO64
封裝： 6.10 MM, 0.50 MM PITCH, ROHS COMPLIANT, MO-153, TSSOP-64
文件頁數(shù)： 10/14頁
文件大?。?/td> 217K
代理商： 9DB1200CGLF
IDTTM/ICSTM
Twelve Output Differential Buffer for PCIe Gen1/Gen2, QPI, and FBDIMM
ICS9DB1200C
Twelve Output Differential Buffer for PCIe Gen1/Gen2, QPI, and FBDIMM
5
1414E—11/04/09
Absolute Max
Electrical Characteristics - Input/Supply/Common Output Parameters
Symbol
Parameter
Min
Max
Units
VDDA
3.3V Core Supply Voltage
4.6
V
VDD
3.3V Logic Supply Voltage
4.6
V
VIL
Input Low Voltage
GND-0.5
V
VIH
Input High Voltage
VDD+0.5V
V
Ts
Storage Temperature
-65
150
°C
Tambient
Ambient Operating Temp
0
70
°C
Tcase
Case Temperature
115
°C
ESD prot
Input ESD protection
human body model
2000
V
TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5%
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS NOTES
Input High Voltage
VIH
3.3 V +/-5%
2
VDD + 0.3
V
1
Input Low Voltage
VIL
3.3 V +/-5%
GND - 0.3
0.8
V
1
Input High Current
IIH
VIN = VDD
-5
5
uA
1
IIL1
VIN = 0 V; Inputs with no pull-up
resistors
-5
uA
1
IIL2
VIN = 0 V; Inputs with pull-up resistors
-200
uA
1
Operating Supply Current
IDD3.3OP
Full Active, CL = Full load;
375
mA
1
Powerdown Current
IDD3.3PD
all differential pairs tri-stated
24
mA
1
FiPLL
PLL Mode
100
400
MHz
1
FiBYPASS
Bypass Mode
33
400
MHz
1
Pin Inductance
Lpin
7nH
1
CIN
Logic Inputs
1.5
5
pF
1
COUT
Output pin capacitance
6
pF
1
Peaking when HIGH_BW#=0
1.5
2
dB
1
Peaking when HIGH_BW#=1
1.5
2
dB
1
PLL Bandwidth when HIGH_BW#=0
2
3
4
MHz
1
PLL Bandwidth when HIGH_BW#=1
0.7
1
1.4
MHz
1
Clk Stabilization
TSTAB
From VDD Power-Up and after input
clock stabilization or de-assertion of
PD# to 1st clock
1.8
ms
1,2
Modulation Frequency
fMOD
Triangular Modulation
30
33
kHz
1
OE# Latency
tLATOE#
DIF start after OE# assertion
DIF stop after OE# deassertion
4
12
cycles
1,3
Tdrive_PD
tDRVPD
DIF output enable after
PD de-assertion
300
us
1,3
Tfall
tF
Fall time of OE#
5
ns
1
Trise
tR
Rise time of OE#
5
ns
1
1Guaranteed by design and characterization, not 100% tested in production.
2See timing diagrams for timing requirements.
3Time from deassertion until outputs are >200 mV
Capacitance
Input Low Current
PLL Bandwidth
BW
Input Frequency
PLL Jitter Peaking
jPEAK
相關(guān)PDF資料
PDF描述
9DB1233AGLF 9DB SERIES, PLL BASED CLOCK DRIVER, 12 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO64
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
9DB1200CGLFT 功能描述:時鐘緩沖器 12 OUTPUT PCIE GEN2 BUFFER w/QPI RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel
9DB1233 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:Twelve Output Differential Buffer for PCIe Gen3
9DB1233AGLF 功能描述:時鐘緩沖器 12 OUTPUT PCIE GEN3 BUFFER RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel
9DB1233AGLFT 功能描述:時鐘緩沖器 12 OUTPUT PCIE GEN3 BUFFER RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel
9DB1904B 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:19 Output Differential Buffer for PCIe Gen2 and QPI
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