參數(shù)資料
型號(hào): 9DB1200CGLF
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類(lèi): 時(shí)鐘及定時(shí)
英文描述: 9DB SERIES, PLL BASED CLOCK DRIVER, 12 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO64
封裝: 6.10 MM, 0.50 MM PITCH, ROHS COMPLIANT, MO-153, TSSOP-64
文件頁(yè)數(shù): 11/14頁(yè)
文件大?。?/td> 217K
代理商: 9DB1200CGLF
IDTTM/ICSTM
Twelve Output Differential Buffer for PCIe Gen1/Gen2, QPI, and FBDIMM
ICS9DB1200C
Twelve Output Differential Buffer for PCIe Gen1/Gen2, QPI, and FBDIMM
6
1414E—11/04/09
Electrical Characteristics - Clock Input Parameters
TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5%
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS NOTES
Input High Voltage -
DIF_IN
VIHDIF
Differential inputs
(single-ended measurement)
600
800
1150
mV
1
Input Low Voltage -
DIF_IN
VILDIF
Differential inputs
(single-ended measurement)
VSS - 300
0
300
mV
1
Input Common Mode
Voltage - DIF_IN
VCOM
Common Mode Input Voltage
300
1000
mV
1
Input Amplitude - DIF_IN
VSWING
Peak to Peak value
300
1450
mV
1
Input Slew Rate - DIF_IN
dv/dt
Measured differentially
0.4
8
V/ns
1,2
Input Leakage Current
IIN
VIN = VDD , VIN = GND
-5
5
uA
1
Input Duty Cycle
dtin
Measurement from differential
wavefrom
45
55
%
1
Input Jitter - Cycle to
Cycle
JDIFIn
Differential Measurement
0
125
ps
1
1 Guaranteed by design and characterization, not 100% tested in production.
2Slew rate measured through Vswing min centered around differential zero
Electrical Characteristics - DIF 0.7V Current Mode Differential Pair
TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL =2pF, RS=33.2, RP=49.9, RREF=475
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS NOTES
Current Source Output
Impedance
Zo
1
VO = Vx
3000
1
Voltage High
VHigh
660
850
1,3
Voltage Low
VLow
-150
150
1,3
Max VoltageVovs
1150
1
Min VoltageVuds
-300
1
Crossing Voltage (abs)
Vcross(abs)
250
550
mV
1
Crossing Voltage (var)
d-Vcross
Variation of crossing over all edges
140
mV
1
Long Accuracy
ppmsee Tperiod min-max values
0
ppm1,2
Rise Time
tr
VOL = 0.175V, VOH = 0.525V
175
700
ps
1
Fall Time
tf
VOH = 0.525V VOL = 0.175V
175
700
ps
1
Rise Time Variation
d-tr
125
ps
1
Fall Time Variation
d-tf
125
ps
1
Duty Cycle
dt3
Measurement from differential wavefrom
45
55
%
1
tpdBYP
Bypass Mode, VT = 50%
2.5
4.5
ps
1
tpdPLL
PLL Mode VT = 50%
-250
250
ps
1
Skew, Output to Output
tsk3
VT = 50%
50
ps
1
PLL mode
50
ps1,5
BYPASS mode as additive jitter
50
ps1,5
1Guaranteed by design and characterization, not 100% tested in production.
3I
REF = VDD/(3xRR). For RR = 475
(1%), I
REF = 2.32mA. IOH = 6 x IREF and VOH = 0.7V @ ZO=50
.
4 Applies to Bypass Mode Only
5 Measured from differential waveform
Skew, Input to Output
2 All Long Term Accuracy specifications are guaranteed with the assumption that the input clock complies with
CK410B+/CK509B accuracy requirements. The 9DB1200 itself does not contribute to ppm error.
Jitter, Cycle to cycle
tjcyc-cyc
Statistical measurement on single ended
signal using oscilloscope math function.
mV
Measurement on single ended signal
using absolute value.
mV
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