參數(shù)資料
型號(hào): 9DB1200CGLF
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: 時(shí)鐘及定時(shí)
英文描述: 9DB SERIES, PLL BASED CLOCK DRIVER, 12 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO64
封裝: 6.10 MM, 0.50 MM PITCH, ROHS COMPLIANT, MO-153, TSSOP-64
文件頁數(shù): 8/14頁
文件大?。?/td> 217K
代理商: 9DB1200CGLF
IDTTM/ICSTM
Twelve Output Differential Buffer for PCIe Gen1/Gen2, QPI, and FBDIMM
ICS9DB1200C
Twelve Output Differential Buffer for PCIe Gen1/Gen2, QPI, and FBDIMM
3
1414E—11/04/09
Pin Description
PIN #
PIN NAME
TYPE
DESCRIPTION
1
VDD
PWR
Power supply, nominal 3.3V
2
DIF_IN
IN
0.7 V Differential TRUE input
3
DIF_IN#
IN
0.7 V Differential Complementary Input
4
GND
PWR
Ground pin.
5OE0#
IN
Active low input for enabling DIF pair 0.
1 = tri-state outputs, 0 = enable outputs
6
DIF_0
OUT
0.7V differential true clock output
7
DIF_0#
OUT
0.7V differential Complementary clock output
8
VDD
PWR
Power supply, nominal 3.3V
9
GND
PWR
Ground pin.
10
OE1#
IN
Active low input for enabling DIF pair 1.
1 = tri-state outputs, 0 = enable outputs
11
DIF_1
OUT
0.7V differential true clock output
12
DIF_1#
OUT
0.7V differential Complementary clock output
13
OE2#
IN
Active low input for enabling DIF pair 2.
1 = tri-state outputs, 0 = enable outputs
14
DIF_2
OUT
0.7V differential true clock output
15
DIF_2#
OUT
0.7V differential Complementary clock output
16
GND
PWR
Ground pin.
17
VDD
PWR
Power supply, nominal 3.3V
18
OE3#
IN
Active low input for enabling DIF pair 3.
1 = tri-state outputs, 0 = enable outputs
19
DIF_3
OUT
0.7V differential true clock output
20
DIF_3#
OUT
0.7V differential Complementary clock output
21
OE4#
IN
Active low input for enabling DIF pair 4
1 = tri-state outputs, 0 = enable outputs
22
DIF_4
OUT
0.7V differential true clock output
23
DIF_4#
OUT
0.7V differential Complementary clock output
24
VDD
PWR
Power supply, nominal 3.3V
25
GND
PWR
Ground pin.
26
OE5#
IN
Active low input for enabling DIF pair 5.
1 = tri-state outputs, 0 = enable outputs
27
DIF_5
OUT
0.7V differential true clock output
28
DIF_5#
OUT
0.7V differential Complementary clock output
29
**ADR_SEL
IN
This tri-level input selects one of 3 SMBus addresses. See the SMBus
Address Select Table for the addresses.
30
HIGH_BW#
IN
3.3V input for selecting PLL Band Width
0 = High, 1= Low
31
FS2
IN
Frequency select pin.
32
SMBCLK
IN
Clock pin of SMBUS circuitry, 5V tolerant
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
9DB1200CGLFT 功能描述:時(shí)鐘緩沖器 12 OUTPUT PCIE GEN2 BUFFER w/QPI RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲(最大值): 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel
9DB1233 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:Twelve Output Differential Buffer for PCIe Gen3
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9DB1233AGLFT 功能描述:時(shí)鐘緩沖器 12 OUTPUT PCIE GEN3 BUFFER RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲(最大值): 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel
9DB1904B 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:19 Output Differential Buffer for PCIe Gen2 and QPI