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參數(shù)資料
| 型號： | 9FG108CGLFT |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘產(chǎn)生/分配 |
| 英文描述： | 400 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| 封裝： | 6.10 MM WIDTH, 0.50 MM PITCH, ROHS COMPLIANT, MO-153, TSSOP-48 |
| 文件頁數(shù)： | 7/21頁 |
| 文件大?。?/td> | 263K |
| 代理商： | 9FG108CGLFT |
IDTTM/ICSTM
Frequency Generator for CPU, FBD, PCIe Gen 1/2 & SATA
ICS9FG108
REV J 02/20/09
ICS9FG108
Frequency Generator for CPU, FBD, PCIe Gen 1/2 & SATA
15
SMBus Table: PLL Frequency Control Register
Pin #
Name
Control Function
Type
0
1
Default
Bit 7
PLL N Div7
RW
X
Bit 6
PLL N Div6
RW
X
Bit 5
PLL N Div5
RW
X
Bit 4
PLL N Div4
RW
X
Bit 3
PLL N Div3
RW
X
Bit 2
PLL N Div2
RW
X
Bit 1
PLL N Div1
RW
X
Bit 0
PLL N Div0
RW
X
SMBus Table: PLL Spread Spectrum Control Register
Pin #
Name
Control Function
Type
0
1
Default
Bit 7
PLL SSP7
RW
X
Bit 6
PLL SSP6
RW
X
Bit 5
PLL SSP5
RW
X
Bit 4
PLL SSP4
RW
X
Bit 3
PLL SSP3
RW
X
Bit 2
PLL SSP2
RW
X
Bit 1
PLL SSP1
RW
X
Bit 0
PLL SSP0
RW
X
SMBus Table: PLL Spread Spectrum Control Register
Pin #
Name
Control Function
Type
0
1
Default
Bit 7
0
Bit 6
PLL SSP14
RW
X
Bit 5
PLL SSP13
RW
X
Bit 4
PLL SSP12
RW
X
Bit 3
PLL SSP11
RW
X
Bit 2
PLL SSP10
RW
X
Bit 1
PLL SSP9
RW
X
Bit 0
PLL SSP8
RW
X
SMBus Table: Reserved Test Register
Pin #
Name
Control Function
Type
0
1
Default
Bit 7
1
Bit 6
0
Bit 5
0
Bit 4
0
Bit 3
0
Bit 2
0
Bit 1
0
Bit 0
0
-
Spread Spectrum
Programming bit(14:8)
These Spread
Spectrum bits in
Byte 13 and 14 will
program the spread
pecentage of PLL
-
Byte 13
-
Reserved
-
Spread Spectrum
Programming bit(7:0)
These Spread
Spectrum bits in
Byte 13 and 14 will
program the spread
pecentage of PLL
-
Byte 12
-
N Divider Programming
Byte11 bit(7:0) and
Byte10 bit(7:6)
The decimal
representation of M and
N Divider in Byte 11 and
12 will configure the PLL
VCO frequency.
Default at power up =
latch-in or Byte 0 Rom
table. VCO Frequency
= fXTAL x [NDiv(9:0)+8]
/ [MDiv(5:0)+2]
-
Byte 11
-
Byte 14
-
Reserved Test Register. Do not write to this register, erratic device
operation may occur.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| 9FG108DFILF | 功能描述:時鐘合成器/抖動清除器 PCIE GEN2 SYNTHESIZER RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| 9FG108DFILFT | 功能描述:時鐘合成器/抖動清除器 PCIE GEN2 SYNTHESIZER RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| 9FG108DFLF | 功能描述:時鐘合成器/抖動清除器 PCIE GEN2 SYNTHESIZER RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| 9FG108DFLFT | 功能描述:時鐘合成器/抖動清除器 PCIE GEN2 SYNTHESIZER RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| 9FG108DGILF | 功能描述:時鐘合成器/抖動清除器 PCIE GEN2 SYNTHESIZER RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
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