參數(shù)資料
型號(hào)： 9FG1901HKLFT
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： 時(shí)鐘產(chǎn)生/分配
英文描述： 200 MHz, PROC SPECIFIC CLOCK GENERATOR, PQCC72
封裝： ROHS COMPLIANT, PLASTIC, MLF-72
文件頁(yè)數(shù)： 17/18頁(yè)
文件大?。?/td> 245K
代理商： 9FG1901HKLFT
IDTTM
Frequency Gearing Clock for CPU, PCIe Gen1 & FBD
1386A - 02/02/10
9FG1901H
Frequency Gearing Clock for CPU, PCIe Gen1 & FBD
8
SMBusTable: FSB Frequency Select Register
Pin #
Name
Control Function
Type0
1
PWD
Bit 7
GRSEL_17
Group of 17 gear ratio select
RW
Gear Ratio
1:1
1
Bit 6
GRSEL_2
Group of 2 gear ratio select
RW
Gear Ratio
1:1
1
Bit 5
X
Bit 4
RW
Latch
Bit 3
FSBG_3
FSB Gear Ratio FS_3
RW
x
Bit 2
FSBG_2
FSB Gear Ratio FS_2
RW
0
Bit 1
FSBG_1
FSB Gear Ratio FS_1
RW
x
Bit 0
FSBG_0
FSB Gear Ratio FS_0
RW
1
SMBusTable: Output Control Register
Pin #
Name
Control Function
Type0
1
PWD
Bit 7
DIF_7
Output Control
RW
Hi-Z
Enable
1
Bit 6
DIF_6
Output Control
RW
Hi-Z
Enable
1
Bit 5
DIF_5
Output Control
RW
Hi-Z
Enable
1
Bit 4
DIF_4
Output Control
RW
Hi-Z
Enable
1
Bit 3
DIF_3
Output Control
RW
Hi-Z
Enable
1
Bit 2
DIF_2
Output Control
RW
Hi-Z
Enable
1
Bit 1
DIF_1
Output Control
RW
Hi-Z
Enable
1
Bit 0
DIF_0
Output Control
RW
Hi-Z
Enable
1
SMBusTable: Output and PLL BW Control Register
Pin #
Name
Control Function
Type0
1
PWD
Bit 7
RW
High BW
Low BW
1
Bit 6
RW
Bypass
PLL
1
Bit 5
DIF_13
Output Control
RW
Hi-Z
Enable
1
Bit 4
DIF_12
Output Control
RW
Hi-Z
Enable
1
Bit 3
DIF_11
Output Control
RW
Hi-Z
Enable
1
Bit 2
DIF_10
Output Control
RW
Hi-Z
Enable
1
Bit 1
DIF_9
Output Control
RW
Hi-Z
Enable
1
Bit 0
DIF_8
Output Control
RW
Hi-Z
Enable
1
Note: Bit 7 is wired OR to the HIGH_BW# input, any 0 selects High BW
Note: Bit 6 is wired OR to the SMB_A2_PLLBYP# input, any 0 selects Fanout Bypass mode
SMBusTable: Output Enable Readback Register
Pin #
Name
Control Function
Type0
1
PWD
Bit 7
R
X
Bit 6
R
X
Bit 5
R
X
Bit 4
R
X
Bit 3
R
X
Bit 2
R
X
Bit 1
R
X
Bit 0
R
X
Readback - SMB_A2_PLLBYP# In
Readback
Readback - HIGH_BW# In
Readback
Byte 2
Readback - OE9# Input
Readback - OE8# Input
see note
BYPASS# test mode / PLL
Byte 3
72
8
Byte 0
DIF(16:0)
DIF(18:17)
FS_A_410 Latched Input
-
Reserved
See ICS9FG1901
Programmable Gear Ratios
Table
-
Byte 1
Readback
see note
PLL_BW# adjust
Readback - OE7# Input
Readback
Readback - OE5# Input
Readback - OE6# Input
Readback
Readback - OE_01234# Input
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