參數(shù)資料
型號: 9FG1901HKLFT
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: 時鐘產(chǎn)生/分配
英文描述: 200 MHz, PROC SPECIFIC CLOCK GENERATOR, PQCC72
封裝: ROHS COMPLIANT, PLASTIC, MLF-72
文件頁數(shù): 18/18頁
文件大?。?/td> 245K
代理商: 9FG1901HKLFT
IDTTM
Frequency Gearing Clock for CPU, PCIe Gen1 & FBD
1386A - 02/02/10
9FG1901H
Frequency Gearing Clock for CPU, PCIe Gen1 & FBD
9
SMBusTable: Output Enable Readback Register
Pin #
Name
Control Function
Type0
1
PWD
Bit 7
R
X
Bit 6
R
X
Bit 5
R
X
Bit 4
R
X
Bit 3
R
X
Bit 2
R
X
Bit 1
R
X
Bit 0
R
X
SMBusTable: Vendor & Revision ID Register
Pin #
Name
Control Function
Type0
1
PWD
Bit 7
RID3
R
-
X
Bit 6
RID2
R
-
X
Bit 5
RID1
R
-
X
Bit 4
RID0
R
-
X
Bit 3
VID3
R
-
0
Bit 2
VID2
R
-
0
Bit 1
VID1
R
-
0
Bit 0
VID0
R
-
1
SMBusTable: DEVICE ID
Pin #
Name
Control Function
Type0
1
PWD
Bit 7
RW
1
Bit 6
RW
0
Bit 5
RW
0
Bit 4
RW
1
Bit 3
RW
0
Bit 2
RW
0
Bit 1
RW
0
Bit 0
RW
1
SMBusTable: Byte Count Register
Pin #
Name
Control Function
Type0
1
PWD
Bit 7
BC7
RW
-
0
Bit 6
BC6
RW
-
0
Bit 5
BC5
RW
-
0
Bit 4
BC4
RW
-
0
Bit 3
BC3
RW
-
0
Bit 2
BC2
RW
-
1
Bit 1
BC1
RW
-
1
Bit 0
BC0
RW
-
1
Readback - OE16# Input
Device ID 7 (MSB)
Readback - OE12# Input
VENDOR ID
Readback - OE11# Input
Readback
Readback - OE15# Input
Readback
Reserved
REVISION ID
Reserved
Device ID 6
Reserved
-
Byte 5
-
Byte 6
60
Byte 4
57
Byte 7
-
Device ID 0
-
Reserved
Readback - OE14# Input
Readback
Readback - OE10# Input
Device ID 5
Reserved
-
Device ID 4
Writing to this register configures
how many bytes will be read
back.
-
Readback
Device ID 3
Readback - OE13# Input
Readback - OE17_18# Input
Readback
Device ID 2
Reserved
Device ID 1
Reserved
69
Readback
54
51
48
43
40
-
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