參數(shù)資料
型號(hào)： 9S12B128DGV1
英文描述： 9S12B128 Device Guide
中文描述： 9S12B128設(shè)備指南
文件頁數(shù)： 119/128頁
文件大?。?/td> 1823K
代理商： 9S12B128DGV1
Device User Guide —9S12B128DGV1/D V01.11
119
A.8 External Bus Timing
A timing diagram of the external multiplexed-bus is illustrated in
Figure A-10
with the actual timing
values shown on
Table A-26
in 5V range. All major bus signals are included in the diagram. While both
a data write and data read cycle are shown, only one or the other would occur on a particular bus cycle.
A.8.1 General Muxed Bus Timing
The expanded bus timings are highly dependent on the load conditions. The timing parameters shown
assume a balanced load across all outputs.
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