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Device User Guide —9S12B128DGV1/D V01.11
9
List of Figures
Figure 0-1
Figure 1-1
Figure 1-2
Figure 1-3
Figure 2-1
Figure 2-2
Figure 2-3
Figure 2-4
Figure 2-5
Figure 2-6
Figure 3-1
Figure 21-1 Recommended PCB Layout 112LQFP Colpitts Oscillator. . . . . . . . . . . . . . . . . .75
Figure 21-2 Recommended PCB Layout for 80QFP Colpitts Oscillator . . . . . . . . . . . . . . . . .76
Figure 21-3 Recommended PCB Layout for 112LQFP Pierce Oscillator . . . . . . . . . . . . . . . .77
Figure 21-4 Recommended PCB Layout for 80QFP Pierce Oscillator . . . . . . . . . . . . . . . . . .78
Figure A-1
ATD Accuracy Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Figure A-2
VREG_3V3 - Chip Power-up and Voltage Drops (not scaled). . . . . . . . . . . . . 102
Figure A-3
Basic PLL functional diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Figure A-4
Jitter Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Figure A-5
Maximum bus clock jitter approximation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Figure A-6
SPI Master Timing (CPHA=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Figure A-7
SPI Master Timing (CPHA=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Figure A-8
SPI Slave Timing (CPHA=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Figure A-9
SPI Slave Timing (CPHA=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Figure A-10 General External Bus Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Figure B-1
112-pin LQFP mechanical dimensions (case no. 987) . . . . . . . . . . . . . . . . . . 124
Figure B-2
80-pin QFP Mechanical Dimensions (case no. 841B). . . . . . . . . . . . . . . . . . . 125
Order Partnumber Example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
MC9S12B128 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
MC9S12B128 Memory Map out of Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
MC9S12B64 using MC9S12B128 die Memory Map out of Reset. . . . . . . . . . . .28
Pin Assignments in 112-pin LQFP for MC9S12B128 . . . . . . . . . . . . . . . . . . . . .48
Pin Assignments in 80-pin QFP for MC9S12B128 . . . . . . . . . . . . . . . . . . . . . . .49
PLL Loop Filter Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
Colpitts Oscillator Connections (PE7=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
Pierce Oscillator Connections (PE7=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
External Clock Connections (PE7=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
Clock Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62