參數(shù)資料
型號(hào)： 9S12DP512DGV1
英文描述： 9S12Dx512 Device Guide
中文描述： 9S12Dx512設(shè)備指南
文件頁數(shù)： 13/126頁
文件大小： 1809K
代理商： 9S12DP512DGV1
MC9S12DJ64 Device User Guide — V01.17
13
List of Tables
Table 0-1
Table 0-2
Table 1-1
$0000 - $000F
$0010 - $0014
$0015 - $0016
$0017 - $0019
$001A - $001B Device ID Register (
Table 1-3
) ................................................................29
$001C - $001D MMC map 3 of 4 (HCS12 Module Mapping Control,
Table 1-4
) ..............29
$001E - $001E MEBI map 2 of 3 (HCS12 Multiplexed External Bus Interface) ................29
$001F - $001F
INT map 2 of 2 (HCS12 Interrupt) ............................................................29
$0020 - $0027
Reserved ..................................................................................................29
$0028 - $002F
BKP (HCS12 Breakpoint) .........................................................................30
$0030 - $0031
MMC map 4 of 4 (HCS12 Module Mapping Control) ...............................30
$0032 - $0033
MEBI map 3 of 3 (HCS12 Multiplexed External Bus Interface) ................30
$0034 - $003F
CRG (Clock and Reset Generator) ..........................................................30
$0040 - $007F
ECT (Enhanced Capture Timer 16 Bit 8 Channels) .................................31
$0080 - $009F
ATD0 (Analog to Digital Converter 10 Bit 8 Channel) ..............................34
$00A0 - $00C7 PWM (Pulse Width Modulator 8 Bit 8 Channel) .......................................35
$00C8 - $00CF SCI0 (Asynchronous Serial Interface) ......................................................37
$00D0 - $00D7 SCI1 (Asynchronous Serial Interface) ......................................................37
$00D8 - $00DF SPI0 (Serial Peripheral Interface) ............................................................37
$00E0 - $00E7 IIC (Inter IC Bus) ......................................................................................38
$00E8 - $00EF BDLC (Bytelevel Data Link Controller J1850) ..........................................38
$00F0 - $00FF Reserved ..................................................................................................39
$0100 - $010F
Flash Control Register (fts64k) ................................................................39
$0110 - $011B
EEPROM Control Register (eets1k) ........................................................39
$011C - $011F Reserved for RAM Control Register ........................................................40
$0120 - $013F
ATD1 (Analog to Digital Converter 10 Bit 8 Channel) ..............................40
$0140 - $017F
CAN0 (Motorola Scalable CAN - MSCAN) ..............................................41
Table 1-2
Detailed MSCAN Foreground Receive and Transmit Buffer Layout . . . . . . . . . . .42
$0180 - $023F
Reserved ..................................................................................................43
$0240 - $027F
PIM (Port Integration Module) ..................................................................44
Derivative Differences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Document References. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Device Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
MEBI map 1 of 3 (HCS12 Multiplexed External Bus Interface) ................28
MMC map 1 of 4 (HCS12 Module Mapping Control) ...............................28
INT map 1 of 2 (HCS12 Interrupt) ............................................................29
Reserved ..................................................................................................29
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