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參數(shù)資料
| 型號： | A1225A-1PQG100I |
| 廠商： | Microsemi SoC |
| 文件頁數(shù)： | 14/54頁 |
| 文件大小： | 0K |
| 描述： | IC FPGA 2500 GATES 100-PQFP IND |
| 產(chǎn)品變化通告： | A1225A Family Discontinuation 18/Apr/2012 |
| 標準包裝： | 66 |
| 系列： | ACT™ 2 |
| LAB/CLB數(shù)： | 451 |
| 輸入/輸出數(shù)： | 83 |
| 門數(shù)： | 2500 |
| 電源電壓： | 4.5 V ~ 5.5 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 100-BQFP |
| 供應商設備封裝： | 100-PQFP（14x20） |
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ACT 2 Family FPGAs
R e visio n 8
2 - 15
A1240A Timing Characteristics
Table 2-15 A1240A Worst-Case Commercial Conditions, VCC = 4.75 V, TJ = 70°C
Logic Module Propagation Delays1
–2 Speed3
–1 Speed
Std. Speed
Units
Parameter/Description
Min.
Max.
Min.
Max.
Min.
Max.
tPD1
Single Module
3.8
4.3
5.0
ns
tCO
Sequential Clock to Q
3.8
4.3
5.0
ns
tGO
Latch G to Q
3.8
4.3
5.0
ns
tRS
Flip-Flop (Latch) Reset to Q
3.8
4.3
5.0
ns
Predicted Routing Delays2
tRD1
FO = 1 Routing Delay
1.4
1.5
1.8
ns
tRD2
FO = 2 Routing Delay
1.7
2.0
2.3
ns
tRD3
FO = 3 Routing Delay
2.3
2.6
3.0
ns
tRD4
FO = 4 Routing Delay
3.1
3.5
4.1
ns
tRD8
FO = 8 Routing Delay
4.7
5.4
6.3
ns
Sequential Timing Characteristics3,4
tSUD
Flip-Flop (Latch) Data Input Setup
0.4
0.5
ns
tHD
Flip-Flop (Latch) Data Input Hold
0.0
ns
tSUENA
Flip-Flop (Latch) Enable Setup
0.8
0.9
1.0
ns
tHENA
Flip-Flop (Latch) Enable Hold
0.0
ns
tWCLKA
Flip-Flop (Latch) Clock Active Pulse Width
4.5
6.0
6.5
ns
tWASYN
Flip-Flop (Latch) Clock Asynchronous Pulse Width
4.5
6.0
6.5
ns
tA
Flip-Flop Clock Input Period
9.8
12.0
15.0
ns
tINH
Input Buffer Latch Hold
0.0
ns
tINSU
Input Buffer Latch Setup
0.4
0.5
ns
tOUTH
Output Buffer Latch Hold
0.0
ns
tOUTSU
Output Buffer Latch Setup
0.4
0.5
ns
fMAX
Flip-Flop (Latch) Clock Frequency
100.0
80.0
66.0
MHz
Notes:
1. For dual-module macros, use tPD1 + tRD1 + tPDn, tCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD —whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for
estimating device performance. Post-route timing analysis or simulation is required to determine actual worst-case
performance. Post-route timing is based on actual routing delay measurements performed on the device prior to
shipment.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules
can be obtained from the DirectTime Analyzer utility.
4. Setup and hold timing parameters for the Input Buffer Latch are defined with respect to the PAD and the D input. External
setup/hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external
PAD signal to the G input subtracts (adds) to the internal setup (hold) time.
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