Table 2-20 A1280A Worst-Case Commercial Conditions, VCC = 4.75 V, T
參數(shù)資料
型號(hào): A1225A-1PQG100I
廠商: Microsemi SoC
文件頁(yè)數(shù): 19/54頁(yè)
文件大?。?/td> 0K
描述: IC FPGA 2500 GATES 100-PQFP IND
產(chǎn)品變化通告: A1225A Family Discontinuation 18/Apr/2012
標(biāo)準(zhǔn)包裝: 66
系列: ACT™ 2
LAB/CLB數(shù): 451
輸入/輸出數(shù): 83
門(mén)數(shù): 2500
電源電壓: 4.5 V ~ 5.5 V
安裝類型: 表面貼裝
工作溫度: -40°C ~ 85°C
封裝/外殼: 100-BQFP
供應(yīng)商設(shè)備封裝: 100-PQFP(14x20)
Detailed Specifications
2- 20
R e visio n 8
Table 2-20 A1280A Worst-Case Commercial Conditions, VCC = 4.75 V, TJ = 70°C
TTL Output Module Timing1
–2 Speed
–1 Speed
Std. Speed
Units
Parameter/Description
Min.
Max.
Min.
Max.
Min.
Max.
tDLH
Data to Pad High
8.1
9.0
10.6
ns
tDHL
Data to Pad Low
10.2
11.4
13.4
ns
tENZH
Enable Pad Z to High
9.0
10.0
11.8
ns
tENZL
Enable Pad Z to Low
11.8
13.2
15.5
ns
tENHZ
Enable Pad High to Z
7.1
8.0
9.4
ns
tENLZ
Enable Pad Low to Z
8.4
9.5
11.1
ns
tGLH
G to Pad High
9.0
10.2
11.9
ns
tGHL
G to Pad Low
11.3
12.7
14.9
ns
dTLH
Delta Low to High
0.07
0.08
0.09
ns/pF
dTHL
Delta High to Low
0.12
0.13
0.16
ns/pF
CMOS Output Module Timing1
tDLH
Data to Pad High
10.3
11.5
13.5
ns
tDHL
Data to Pad Low
8.5
9.6
11.2
ns
tENZH
Enable Pad Z to High
9.0
10.0
11.8
ns
tENZL
Enable Pad Z to Low
11.8
13.2
15.5
ns
tENHZ
Enable Pad High to Z
7.1
8.0
9.4
ns
tENLZ
Enable Pad Low to Z
8.4
9.5
11.1
ns
tGLH
G to Pad High
9.0
10.2
11.9
ns
tGHL
G to Pad Low
11.3
12.7
14.9
ns
dTLH
Delta Low to High
0.12
0.13
0.16
ns/pF
dTHL
Delta High to Low
0.09
0.10
0.12
ns/pF
Notes:
1. Delays based on 50 pF loading.
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