Table 2-16 A1240A Worst-Case Commercial Condit" />
參數資料
型號: A1280A-1PL84I
廠商: Microsemi SoC
文件頁數: 15/54頁
文件大?。?/td> 0K
描述: IC FPGA 8K GATES 84-PLCC IND
標準包裝: 16
系列: ACT™ 2
LAB/CLB數: 1232
輸入/輸出數: 72
門數: 8000
電源電壓: 4.5 V ~ 5.5 V
安裝類型: 表面貼裝
工作溫度: -40°C ~ 85°C
封裝/外殼: 84-LCC(J 形引線)
供應商設備封裝: 84-PLCC(29.31x29.31)
Detailed Specifications
2- 16
R e visio n 8
A1240A Timing Characteristics (continued)
Table 2-16 A1240A Worst-Case Commercial Conditions, VCC = 4.75 V, TJ = 70°C
I/O Module Input Propagation Delays
–2 Speed
–1 Speed
Std. Speed
Units
Parameter/Description
Min.
Max.
Min.
Max.
Min.
Max.
tINYH
Pad to Y High
2.9
3.3
3.8
ns
tINYL
Pad to Y Low
2.6
3.0
3.5
ns
tINGH
G to Y High
5.0
5.7
6.6
ns
tINGL
G to Y Low
4.7
5.4
6.3
ns
Input Module Predicted Input Routing Delays*
tIRD1
FO = 1 Routing Delay
4.2
4.8
5.6
ns
tIRD2
FO = 2 Routing Delay
4.8
5.4
6.4
ns
tIRD3
FO = 3 Routing Delay
5.4
6.1
7.2
ns
tIRD4
FO = 4 Routing Delay
5.9
6.7
7.9
ns
tIRD8
FO = 8 Routing Delay
7.9
8.9
10.5
ns
Global Clock Network
tCKH
Input Low to High
FO = 32
10.2
11.0
12.8
ns
FO = 256
11.8
13.0
15.7
tCKL
Input High to Low
FO = 32
10.2
11.0
12.8
ns
FO = 256
12.0
13.2
15.9
tPWH
Minimum Pulse Width High
FO = 32
3.8
4.5
5.5
ns
FO = 256
4.1
5.0
5.8
tPWL
Minimum Pulse Width Low
FO = 32
3.8
4.5
5.5
ns
FO = 256
4.1
5.0
5.8
tCKSW
Maximum Skew
FO = 32
0.5
ns
FO = 256
2.5
tSUEXT
Input Latch External Setup
FO = 32
0.0
ns
FO = 256
0.0
tHEXT
Input Latch External Hold
FO = 32
7.0
ns
FO = 256
11.2
tP
Minimum Period
FO = 32
8.1
9.1
11.1
ns
FO = 256
8.8
10.0
11.7
fMAX
Maximum Frequency
FO = 32
125.0
110.0
90.0
ns
FO = 256
115.0
100.0
85.0
Note:
*These parameters should be used for estimating device performance. Optimization techniques may further
reduce delays by 0 to 4 ns. Routing delays are for typical designs across worst-case operating conditions. Post-
route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is
based on actual routing delay measurements performed on the device prior to shipment.
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