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參數(shù)資料
| 型號(hào)： | A14100A-1CQ256C |
| 廠商： | Microsemi SoC |
| 文件頁數(shù)： | 3/90頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FPGA 10K GATES 256-CQFP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | ACT™ 3 |
| LAB/CLB數(shù)： | 1377 |
| 輸入/輸出數(shù)： | 228 |
| 門數(shù)： | 10000 |
| 電源電壓： | 4.5 V ~ 5.5 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | 0°C ~ 70°C |
| 封裝/外殼： | 256-BFCQFP，帶拉桿 |
| 供應(yīng)商設(shè)備封裝： | 256-CQFP（75x75） |
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Accelerator Series FPGAs – ACT 3 Family
R e visio n 3
2 -3
The S-module contains a full implementation of the C-module plus a clearable sequential element that
can either implement a latch or flip-flop function. The S-module can therefore implement any function
implemented by the C-module. This allows complex combinatorial-sequential functions to be
implemented with no delay penalty. The Designer Series Development System will automatically
combine any C-module macro driving an S-module macro into the S-module, thereby freeing up a logic
module and eliminating a module delay.
The clear input CLR is accessible from the routing channel. In addition, the clock input may be connected
to one of three clock networks: CLKA, CLKB, or HCLK. The C-module and S-module functional
descriptions are shown in Figure 2-2 and Figure 2-3 on page 2-2. The clock selection is determined by a
multiplexer select at the clock input to the S-module.
I/Os
I/O Modules
I/O modules provide an interface between the array and the I/O Pad Drivers. I/O modules are located in
the array and access the routing channels in a similar fashion to logic modules. The I/O module
schematic is shown in Figure 4. The signals DataIn and DataOut connect to the I/O pad driver.
Each I/O module contains two D-type flip-flops. Each flip-flop is connected to the dedicated I/O clock
(IOCLK). Each flip-flop can be bypassed by nonsequential I/Os. In addition, each flip-flop contains a data
enable input that can be accessed from the routing channels (ODE and IDE). The asynchronous
preset/clear input is driven by the dedicated preset/clear network (IOPCL). Either preset or clear can be
selected individually on an I/O module by I/O module basis.
Figure 2-4
Functional Diagram for I/O Module
D
DATAOUT
D
Q
CLR/PRE
DATAIN
IOCLK
IOPCL
Y
D
Q
CLR/PRE
ODE
MUX
1
0
MUX
1
0
MUX
0
1
MUX
3
0
1
2
S1
S0
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| A14100A-1CQ256E | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:HiRel FPGAs |
| A14100A-1CQ256M | 制造商:Microsemi Corporation 功能描述:FPGA ACT 3 Family 10K Gates 1377 Cells 125MHz 0.8um Technology 5V 256-Pin CQFP 制造商:Microsemi Corporation 功能描述:FPGA ACT 3 10K GATES 1377 CELLS 125MHZ 0.8UM 5V 256CQFP - Trays 制造商:Microsemi Corporation 功能描述:IC FPGA 10K GATES 256-CQFP MIL |
| A14100A-1PG256B | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:HiRel FPGAs |
| A14100A-1PG256C | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:HiRel FPGAs |
| A14100A-1PG256E | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:HiRel FPGAs |
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