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參數(shù)資料
| 型號： | A1460A-1TQG176I |
| 廠商： | Microsemi SoC |
| 文件頁數(shù)： | 6/90頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FPGA 6K GATES 176-TQFP |
| 標準包裝： | 40 |
| 系列： | ACT™ 3 |
| LAB/CLB數(shù)： | 848 |
| 輸入/輸出數(shù)： | 151 |
| 門數(shù)： | 6000 |
| 電源電壓： | 4.5 V ~ 5.5 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 176-LQFP |
| 供應(yīng)商設(shè)備封裝： | 176-TQFP（24x24） |
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Detailed Specifications
2- 6
R e v ision 3
Horizontal Routing
Horizontal channels are located between the rows of modules and are composed of several routing
tracks. The horizontal routing tracks within the channel are divided into one or more segments. The
minimum horizontal segment length is the width of a module-pair, and the maximum horizontal segment
length is the full length of the channel. Any segment that spans more than one-third the row length is
considered a long horizontal segment. A typical channel is shown in Figure 2-7. Undedicated horizontal
routing tracks are used to route signal nets. Dedicated routing tracks are used for the global clock
networks and for power and ground tie-off tracks.
Vertical Routing
Other tracks run vertically through the modules. Vertical tracks are of three types: input, output, and long.
Vertical tracks are also divided into one or more segments. Each segment in an input track is dedicated
to the input of a particular module. Each segment in an output track is dedicated to the output of a
particular module. Long segments are uncommitted and can be assigned during routing. Each output
segment spans four channels (two above and two below), except near the top and bottom of the array
where edge effects occur. LVTs contain either one or two segments. An example of vertical routing tracks
and segments is shown in Figure 2-8.
Figure 2-7
Horizontal Routing Tracks and Segments
Figure 2-8
Vertical Routing Tracks and Segments
HF
Module Row
HCLK
CLK0
NVCC
SIGNAL
(LHT)
SIGNAL
NVSS
CLK1
Track
Segment
|
Module Row
Vertical Input
Segment
S-Module
C-Module
VF
FF
XF
Module Row
Channel
LVTs
S-Module
C-Module
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