參數(shù)資料
型號： A14V100A-RQ208C
廠商： Microsemi SoC
文件頁數(shù)： 22/90頁
文件大?。?/td> 0K
描述： IC FPGA 10K GATES 3.3V 208-PQFP
標(biāo)準(zhǔn)包裝： 24
系列： ACT™ 3
LAB/CLB數(shù)： 1377
輸入/輸出數(shù)： 175
門數(shù)： 10000
電源電壓： 3 V ~ 3.6 V
安裝類型： 表面貼裝
工作溫度： 0°C ~ 70°C
封裝/外殼： 208-BFQFP 裸露焊盤
供應(yīng)商設(shè)備封裝： 208-RQFP（28x28）
Accelerator Series FPGAs – ACT 3 Family
R e visio n 3
2 - 21
Timing Derating
ACT 3 devices are manufactured in a CMOS process. Therefore, device performance varies according
to temperature, voltage, and process variations. Minimum timing parameters reflect maximum operating
voltage, minimum operating temperature, and best-case processing. Maximum timing parameters reflect
minimum operating voltage, maximum operating temperature, and worst-case processing.
Table 2-15 Timing Derating Factor (Temperature and Voltage)
(Commercial Minimum/Maximum Specification) x
Industrial
Military
Min.
Max.
Min.
Max.
0.66
1.07
0.63
1.17
Table 2-16 Timing Derating Factor for Designs at Typical Temperature (TJ = 25°C)
and Voltage (5.0 V)
(Commercial Maximum Specification) x
0.85
Table 2-17 Temperature and Voltage Derating Factors
(normalized to Worst-Case Commercial, TJ = 4.75 V, 70°C)
–55
–40
0
257085
125
4.50
0.72
0.76
0.85
0.90
1.04
1.07
1.117
4.75
0.70
0.73
0.82
0.87
1.00
1.03
1.12
5.00
0.68
0.71
0.79
0.84
0.97
1.00
1.09
5.25
0.66
0.69
0.77
0.82
0.94
0.97
1.06
5.50
0.63
0.66
0.74
0.79
0.90
0.93
1.01
Note:
This derating factor applies to all routing and propagation delays.
Figure 2-18 Junction Temperature and Voltage Derating Curves
(normalized to Worst-Case Commercial, TJ = 4.75 V, 70°C)
Voltage (V)
Derating
F
actor
0.60
0.70
0.80
0.90
1.00
1.10
1.20
4.50
4.75
5.00
5.25
5.50
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