Table 2-34 A14100A, A14V100A Worst-Case Commerc" />
參數(shù)資料
型號(hào)： A14V100A-RQ208C
廠商： Microsemi SoC
文件頁(yè)數(shù)： 41/90頁(yè)
文件大?。?/td> 0K
描述： IC FPGA 10K GATES 3.3V 208-PQFP
標(biāo)準(zhǔn)包裝： 24
系列： ACT™ 3
LAB/CLB數(shù)： 1377
輸入/輸出數(shù)： 175
門(mén)數(shù)： 10000
電源電壓： 3 V ~ 3.6 V
安裝類(lèi)型： 表面貼裝
工作溫度： 0°C ~ 70°C
封裝/外殼： 208-BFQFP 裸露焊盤(pán)
供應(yīng)商設(shè)備封裝： 208-RQFP（28x28）
Detailed Specifications
2- 38
R e visio n 3
A14100A, A14V100A Timing Characteristics
Table 2-34 A14100A, A14V100A Worst-Case Commercial Conditions, VCC = 4.75 V, TJ = 70°C
1
Logic Module Propagation Delays2
–3 Speed3
–2 Speed 3
–1 Speed
Std. Speed
3.3 V Speed1 Units
Parameter/Description
Min.
Max.
Min. Max. Min.
Max.
Min.
Max.
Min.
Max.
tPD
Internal Array Module
2.0
2.3
2.6
3.0
3.9
ns
tCO
Sequential Clock to Q
2.0
2.3
2.6
3.0
3.9
ns
tCLR
Asynchronous Clear to Q
2.0
2.3
2.6
3.0
3.9
ns
Predicted Routing Delays4
tRD1
FO = 1 Routing Delay
0.9
1.0
1.1
1.3
1.7
ns
tRD2
FO = 2 Routing Delay
1.2
1.4
1.6
1.8
2.4
ns
tRD3
FO = 3 Routing Delay
1.4
1.6
1.8
2.1
2.8
ns
tRD4
FO = 4 Routing Delay
1.7
1.9
2.2
2.5
3.3
ns
tRD8
FO = 8 Routing Delay
2.8
3.2
3.6
4.2
5.5
ns
Logic Module Sequential Timing
tSUD
Flip-Flop Data Input Setup
0.5
0.6
0.8
ns
tHD
Flip-Flop Data Input Hold
0.0
0.5
ns
tSUD
Latch Data Input Setup
0.5
0.6
0.8
ns
tHD
Latch Data Input Hold
0.0
0.5
ns
tWASYN Asynchronous Pulse Width
2.4
3.2
3.8
4.8
6.5
ns
tWCLKA Flip-Flop Clock Pulse Width
2.4
3.2
3.8
4.8
6.5
ns
tA
Flip-Flop Clock Input Period
5.0
6.8
8.0
10.0
13.4
ns
fMAX
Flip-Flop Clock Frequency
200
150
125
100
75
MHz
Notes:
1. VCC = 3.0 V for 3.3 V specifications.
2. For dual-module macros, use tPD + tRD1 + tPDn + tCO + tRD1 + tPDn or tPD1 + tRD1 + tSUD, whichever is appropriate.
3. The –2 and –3 speed grades have been discontinued. Refer to PDN 0104, PDN 0203, PDN 0604, and PDN 1004 at
4. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for
estimating device performance. Post-route timing analysis or simulation is required to determine actual worst-case
performance. Post-route timing is based on actual routing delay measurements performed on the device prior to
shipment.
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