參數(shù)資料
型號(hào): A14V60A-TQG176C
廠商: Microsemi SoC
文件頁(yè)數(shù): 4/90頁(yè)
文件大小: 0K
描述: IC FPGA 6K GATES 3.3V 176-TQFP
標(biāo)準(zhǔn)包裝: 40
系列: ACT™ 3
LAB/CLB數(shù): 848
輸入/輸出數(shù): 151
門(mén)數(shù): 6000
電源電壓: 3 V ~ 3.6 V
安裝類(lèi)型: 表面貼裝
工作溫度: 0°C ~ 70°C
封裝/外殼: 176-LQFP
供應(yīng)商設(shè)備封裝: 176-TQFP(24x24)
Detailed Specifications
2- 4
R e v ision 3
The I/O module output Y is used to bring Pad signals into the array or to feed the output register back into
the array. This allows the output register to be used in high-speed state machine applications. Side I/O
modules have a dedicated output segment for Y extending into the routing channels above and below
(similar to logic modules). Top/Bottom I/O modules have no dedicated output segment. Signals coming
into the chip from the top or bottom are routed using F-fuses and LVTs (F-fuses and LVTs are explained
in detail in the routing section).
I/O Pad Drivers
All pad drivers are capable of being tristate. Each buffer connects to an associated I/O module with four
signals: OE (Output Enable), IE (Input Enable), DataOut, and DataIn. Certain special signals used only
during programming and test also connect to the pad drivers: OUTEN (global output enable), INEN
(global input enable), and SLEW (individual slew selection). See Figure 2-5.
Special I/Os
The special I/Os are of two types: temporary and permanent. Temporary special I/Os are used during
programming and testing. They function as normal I/Os when the MODE pin is inactive. Permanent
special I/Os are user programmed as either normal I/Os or special I/Os. Their function does not change
once the device has been programmed. The permanent special I/Os consist of the array clock input
buffers (CLKA and CLKB), the hard-wired array clock input buffer (HCLK), the hard-wired I/O clock input
buffer (IOCLK), and the hard-wired I/O register preset/clear input buffer (IOPCL). Their function is
determined by the I/O macros selected.
Clock Networks
The ACT 3 architecture contains four clock networks: two high-performance dedicated clock networks
and two general purpose routed networks. The high-performance networks function up to 200 MHz,
while the general purpose routed networks function up to 150 MHz.
Figure 2-5
Function Diagram for I/O Pad Driver
PAD
OE
SLEW
DATAOUT
DATAIN
IEN
INEN
OUTEN
相關(guān)PDF資料
PDF描述
A14V60A-TQ176C IC FPGA 6K GATES 3.3V 176-TQFP
ASC49DRTF-S13 CONN EDGECARD 98POS .100 EXTEND
AMC49DRTF-S13 CONN EDGECARD 98POS .100 EXTEND
ASC49DREF-S13 CONN EDGECARD 98POS .100 EXTEND
170-037-173L030 CONN DB37 CRIMP MALE NICKEL
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
A15 制造商:Industrial Timer Company (ITC) 功能描述:Timer-Counter Display Panel
A15 14 320 制造商:Okw Enclosures 功能描述:Bulk
A-15.360MHZ-18 制造商:Raltron Electronics Corporation 功能描述:
A15/16A 制造商:MISCELLANEOUS 功能描述:
A150 功能描述:ANT A-BASE VHF 1/4 WAVE CHROME RoHS:是 類(lèi)別:RF/IF 和 RFID >> RF 天線 系列:- 標(biāo)準(zhǔn)包裝:1 系列:*