參數(shù)資料
型號(hào)： A14V60A-TQG176C
廠商： Microsemi SoC
文件頁(yè)數(shù)： 7/90頁(yè)
文件大?。?/td> 0K
描述： IC FPGA 6K GATES 3.3V 176-TQFP
標(biāo)準(zhǔn)包裝： 40
系列： ACT™ 3
LAB/CLB數(shù)： 848
輸入/輸出數(shù)： 151
門(mén)數(shù)： 6000
電源電壓： 3 V ~ 3.6 V
安裝類(lèi)型： 表面貼裝
工作溫度： 0°C ~ 70°C
封裝/外殼： 176-LQFP
供應(yīng)商設(shè)備封裝： 176-TQFP（24x24）
Accelerator Series FPGAs – ACT 3 Family
R e visio n 3
2 -7
Antifuse Connections
An antifuse is a “normally open” structure as opposed to the normally closed fuse structure used in
PROMs or PALs. The use of antifuses to implement a programmable logic device results in highly
testable structures as well as an efficient programming architecture. The structure is highly testable
because there are no preexisting connections; temporary connections can be made using pass
transistors. These temporary connections can isolate individual antifuses to be programmed as well as
isolate individual circuit structures to be tested. This can be done both before and after programming. For
example, all metal tracks can be tested for continuity and shorts between adjacent tracks, and the
functionality of all logic modules can be verified.
Four types of antifuse connections are used in the routing structure of the ACT 3 array. (The physical
structure of the antifuse is identical in each case; only the usage differs.)
Table 2-1 shows four types of antifuses.
Examples of all four types of connections are shown in Figure 2-7 on page 2-6 and Figure 2-8 on
Module Interface
Connections to Logic and I/O modules are made through vertical segments that connect to the module
inputs and outputs. These vertical segments lie on vertical tracks that span the entire height of the array.
Module Input Connections
The tracks dedicated to module inputs are segmented by pass transistors in each module row. During
normal user operation, the pass transistors are inactive, which isolates the inputs of a module from the
inputs of the module directly above or below it. During certain test modes, the pass transistors are active
to verify the continuity of the metal tracks. Vertical input segments span only the channel above or the
channel below. The logic modules are arranged such that half of the inputs are connected to the channel
above and half of the inputs to segments in the channel below, as shown in Figure 2-9.
Table 2-1 Antifuse Types
Type
Description
XF
Horizontal-to-vertical connection
HF
Horizontal-to-horizontal connection
VF
Vertical-to-vertical connection
FF
"Fast" vertical connection
Figure 2-9
Logic Module Routing Interface
Y+2
Y+1
A1 D10 D11
B1 B0
D01 D00
Y-1
Y-2
LVTs
Y+2
Y+1
Y
Y-1
Y-2
C-Modules
S-Modules
D10
B0
A0 D11 A1
B1 D01
A0
Y
相關(guān)PDF資料
PDF描述
A14V60A-TQ176C IC FPGA 6K GATES 3.3V 176-TQFP
ASC49DRTF-S13 CONN EDGECARD 98POS .100 EXTEND
AMC49DRTF-S13 CONN EDGECARD 98POS .100 EXTEND
ASC49DREF-S13 CONN EDGECARD 98POS .100 EXTEND
170-037-173L030 CONN DB37 CRIMP MALE NICKEL
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