
A28F400BX-T/B
1.0
PRODUCT FAMILY OVERVIEW
Throughout this datasheet the A28F400BX refers to
both the A28F400BX-T and A28F400BX-B devices.
Section 1 provides an overview of the 4-Mbit flash
memory family including applications, pinouts and
pin descriptions. Section 2 describes in detail the
specific memory organization for the A28F400BX.
Section 3 provides a description of the family’s prin-
ciples of operations. Finally the family’s operating
specifications are described.
1.1 Main Features
The A28F400BX boot block flash memory family is a
very high performance 4-Mbit (4,194,304 bit) memo-
ry family organized as either 256-KWords (262,144
words) of 16 bits each or 512-Kbytes (524,288
bytes) of 8 bits each.
Seven Separately Erasable Blocks
including a
Hardware-Lockable boot block
(16,384 Bytes),
Two parameter blocks
(8,192 Bytes each) and
Four main blocks
(1 block of 98,304 Bytes and 3
blocks of 131,072 Bytes) are included on the 4-Mbit
family. An erase operation erases one of the main
blocks in typically 3 seconds and the boot or param-
eter blocks in typically 1.5 seconds independent of
the remaining blocks. Each block can be indepen-
dently erased and programmed 1,000 times.
The Boot Block
is located at either the top
(A28F400BX-T) or the bottom (A28F400BX-B) of the
address map in order to accommodate different mi-
croprocessor protocols for boot code location. The
hardware lockable boot block
provides the most
secure code storage. The boot block is intended to
store the kernel code required for booting-up a sys-
tem. When the
RP
Y
pin is between 11.4V and 12.6V
the boot block is unlocked and program and erase
operations can be performed. When the RP
Y
pin is
at or below 6.5V the boot block is locked and pro-
gram and erase operations to the boot block are
ignored.
The A28F400BX products are available in the ROM/
EPROM compatible pinout and housed in the
44-Lead PSOP (Plastic Small Outline) package as
shown in Figure 3.
The
Command User Interface (CUI)
serves as the
interface between the microprocessor or microcon-
troller and the internal operation of the A28F400BX
flash memory.
Program and Erase Automation
allows program
and erase operations to be executed using a two-
write command sequence to the CUI. The internal
Write State Machine (WSM) automatically executes
the algorithms and timings necessary for program
and erase operations, including verifications, there-
by unburdening the microprocessor or microcontrol-
ler. Writing of memory data is performed in word or
byte increments typically within 9
m
s which is a
100% improvement over previous flash memory
products.
The
Status Register (SR)
indicates the status of the
WSM and whether the WSM successfully completed
the desired program or erase operation.
Maximum Access Time of
90 ns (TACC)
is achieved
over the automotive temperature range, 10% V
CC
supply range (4.5V to 5.5V) and 100 pF output load.
I
PP
maximum Program current is 40 mA for x16
operation and 30 mA for x8 operation. I
PP
Erase
current is 30 mA maximum. V
PP
erase and pro-
gramming voltage is 11.4V to 12.6V (V
PP
e
12V
g
5%) under all operating conditions. Typical
I
CC
Active Current of 25 mA
is achieved.
The 4-Mbit boot block flash memory family is also
designed with an Automatic Power Savings (APS)
feature to minimize system battery current drain and
allows for very low power designs. Once the device
is accessed to read array data, APS mode will imme-
diately put the memory in static mode of operation
where I
CC
active current is typically 1 mA until the
next read is initiated.
When the CE
Y
and RP
Y
pins are at V
CC
and the
BYTE
Y
pin is at either V
CC
or GND the
CMOS
Standby
mode is enabled where
I
CC
is typically
80
m
A.
A
Deep Power-Down Mode
is enabled when the
RP
Y
pin is at ground minimizing power consumption
and providing write protection during power-up con-
ditions.
I
CC
current
during deep power-down mode
is
50
m
A typical
. An initial maximum access time or
Reset Time of 300 ns is required from RP
Y
switch-
ing until outputs are valid. Equivalently, the device
has a maximum wake-up time of 210 ns until writes
to the Command User Interface are recognized.
When RP
Y
is at ground the WSM is reset, the
Status Register is cleared and the entire device is
protected from being written to. This feature pre-
vents data corruption and protects the code stored
in the device during system reset. The system Reset
pin can be tied to RP
Y
to reset the memory to nor-
mal read mode upon activation of the Reset pin.
With on-chip program/erase automation in the
4-Mbit family and the RP
Y
functionality for data pro-
tection, when the CPU is reset and even if a program
or erase command is issued, the device will not rec-
ognize any operation until RP
Y
returns to its normal
state.
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