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ProASIC3 Flash Family FPGAs
Revision 13
2-81
Figure 2-24 Timing Model and Waveforms
tPD
A
B
tPD = MAX(tPD(RR), tPD(RF), tPD(FF), tPD(FR))
where edges are applicable for the particular
combinatorial cell
Y
NAND2 or
Any Combinatorial
Logic
tPD
50%
VCC
50%
GND
A, B, C
50%
(RR)
(RF)
GND
OUT
GND
50%
(FF)
(FR)
tPD
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