2-12 Revision 13 Total Dynamic Power Consumption鈥擯DYN
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鍨嬭櫉锛� A3P600-FG484I
寤犲晢锛� Microsemi SoC
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鏂囦欢澶у皬锛� 0K
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ProASIC3 DC and Switching Characteristics
2-12
Revision 13
Total Dynamic Power Consumption鈥擯DYN
PDYN = PCLOCK + PS-CELL + PC-CELL + PNET + PINPUTS + POUTPUTS + PMEMORY + PPLL
Global Clock Contribution鈥擯CLOCK
PCLOCK = (PAC1 + NSPINE*PAC2 + NROW*PAC3 + NS-CELL* PAC4) * FCLK
NSPINE is the number of global spines used in the user design鈥攇uidelines are provided in the
"Spine Architecture" section of the Global Resources chapter in the ProASIC3 FPGA
NROW is the number of VersaTile rows used in the design鈥攇uidelines are provided in the "Spine
Architecture" section of the Global Resources chapter in the ProASIC3 FPGA Fabric
FCLK is the global clock signal frequency.
NS-CELL is the number of VersaTiles used as sequential modules in the design.
PAC1, PAC2, PAC3, and PAC4 are device-dependent.
Sequential Cells Contribution鈥擯S-CELL
PS-CELL = NS-CELL * (PAC5 + 1 / 2 * PAC6) * FCLK
NS-CELL is the number of VersaTiles used as sequential modules in the design. When a multi-tile
sequential cell is used, it should be accounted for as 1.
1 is the toggle rate of VersaTile outputs鈥攇uidelines are provided in Table 2-16 on page 2-13.
FCLK is the global clock signal frequency.
Combinatorial Cells Contribution鈥擯C-CELL
PC-CELL = NC-CELL* 1 / 2 * PAC7 * FCLK
NC-CELL is the number of VersaTiles used as combinatorial modules in the design.
1 is the toggle rate of VersaTile outputs鈥攇uidelines are provided in Table 2-16 on page 2-13.
FCLK is the global clock signal frequency.
Routing Net Contribution鈥擯NET
PNET = (NS-CELL + NC-CELL) * 1 / 2 * PAC8 * FCLK
NS-CELL is the number of VersaTiles used as sequential modules in the design.
NC-CELL is the number of VersaTiles used as combinatorial modules in the design.
1 is the toggle rate of VersaTile outputs鈥攇uidelines are provided in Table 2-16 on page 2-13.
FCLK is the global clock signal frequency.
I/O Input Buffer Contribution鈥擯INPUTS
PINPUTS = NINPUTS * 2 / 2 * PAC9 * FCLK
NINPUTS is the number of I/O input buffers used in the design.
2 is the I/O buffer toggle rate鈥攇uidelines are provided in Table 2-16 on page 2-13.
FCLK is the global clock signal frequency.
I/O Output Buffer Contribution鈥擯OUTPUTS
POUTPUTS = NOUTPUTS * 2 / 2 * 1 * PAC10 * FCLK
NOUTPUTS is the number of I/O output buffers used in the design.
2 is the I/O buffer toggle rate鈥攇uidelines are provided in Table 2-16 on page 2-13.
1 is the I/O buffer enable rate鈥攇uidelines are provided in Table 2-17 on page 2-13.
FCLK is the global clock signal frequency.
鐩搁棞PDF璩囨枡
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