Revision 13 2-51 LVPECL Low-Voltage Positive Emitter-Coupled Logic (LVPECL) is another differential I/O standa" />
參數(shù)資料
型號(hào)： A3PE3000-FGG896I
廠商： Microsemi SoC
文件頁數(shù)： 125/162頁
文件大?。?/td> 0K
描述： IC FPGA 1KB FLASH 3M 896-FBGA
標(biāo)準(zhǔn)包裝： 27
系列： ProASIC3E
RAM 位總計(jì)： 516096
輸入/輸出數(shù)： 620
門數(shù)： 3000000
電源電壓： 1.425 V ~ 1.575 V
安裝類型： 表面貼裝
工作溫度： -40°C ~ 85°C
封裝/外殼： 896-BGA
供應(yīng)商設(shè)備封裝： 896-FBGA（31x31）
ProASIC3E Flash Family FPGAs
Revision 13
2-51
LVPECL
Low-Voltage Positive Emitter-Coupled Logic (LVPECL) is another differential I/O standard. It requires
that one data bit be carried through two signal lines. Like LVDS, two pins are needed. It also requires
external resistor termination.
The full implementation of the LVDS transmitter and receiver is shown in an example in Figure 2-24. The
building blocks of the LVPECL transmitter-receiver are one transmitter macro, one receiver macro, three
board resistors at the transmitter end, and one resistor at the receiver end. The values for the three driver
resistors are different from those used in the LVDS implementation because the output standard
specifications are different.
Timing Characteristics
Figure 2-24 LVPECL Circuit Diagram and Board-Level Implementation
Table 2-81 Minimum and Maximum DC Input and Output Levels
DC Parameter
Description
Min.
Max.
Min.
Max.
Min.
Max.
Units
VCCI
Supply Voltage
3.0
3.3
3.6
V
VOL
Output Low Voltage
0.96
1.27
1.06
1.43
1.30
1.57
V
VOH
Output High Voltage
1.8
2.11
1.92
2.28
2.13
2.41
V
VIL, VIH
Input Low, Input High Voltages
0
3.6
0
3.6
0
3.6
V
VODIFF
Differential Output Voltage
0.625
0.97
0.625
0.97
0.625
0.97
V
VOCM
Output Common-Mode Voltage
1.762
1.98
1.762
1.98
1.762
1.98
V
VICM
Input Common-Mode Voltage
1.01
2.57
1.01
2.57
1.01
2.57
V
VIDIFF
Input Differential Voltage
300
mV
Table 2-82 AC Waveforms, Measuring Points, and Capacitive Loads
Input Low (V)
Input High (V)
Measuring Point* (V)
VREF (typ.) (V)
1.64
1.94
Cross point
–
Note: *Measuring point = Vtrip. See Table 2-15 on page 2-18 for a complete table of trip points.
187 W
100
Z0 = 50
100
100
+
–
P
N
P
N
INBUF_LVPECL
OUTBUF_LVPECL
FPGA
Bourns Part Number: CAT16-PC4F12
Table 2-83 LVPECL
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V
Speed Grade
tDOUT
tDP
tDIN
tPY
Units
Std.
0.66
1.83
0.04
1.63
ns
–1
0.56
1.55
0.04
1.39
ns
–2
0.49
1.36
0.03
1.22
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values.
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