2-18 Revision 11 Table 2-18 Summary of I/O Timing Characteristics—Software Default Settings" />
參數(shù)資料
型號: A3PN030-Z2QNG68
廠商: Microsemi SoC
文件頁數(shù): 41/114頁
文件大?。?/td> 0K
描述: IC FPGA NANO 30K GATES 68-QFN
標準包裝: 260
系列: ProASIC3 nano
輸入/輸出數(shù): 49
門數(shù): 30000
電源電壓: 1.425 V ~ 1.575 V
安裝類型: 表面貼裝
工作溫度: 0°C ~ 70°C
封裝/外殼: 68-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 68-QFN(8x8)
ProASIC3 nano DC and Switching Characteristics
2-18
Revision 11
Table 2-18 Summary of I/O Timing Characteristics—Software Default Settings (at 35 pF)
STD Speed Grade, Commercial-Case Conditions: TJ = 70°C, Worst Case VCC = 1.425 V
For A3PN060, A3PN125, and A3PN250
I/O Standard
D
rive
S
tre
ng
th
(mA)
Eq
ui
va
le
nt
Sof
twar
eDefau
lt
D
rive
S
tre
ng
th
Op
tio
n
1
Slew
Rate
C
ap
a
citive
L
o
a
d
(pF
)
t DO
U
T
(ns)
t DP
(ns)
t DI
N
(ns)
t PY
(ns)
t PYS
(ns)
t EOUT
(ns)
t ZL
(ns)
t ZH
(ns)
t LZ
(ns)
t HZ
(ns)
3.3 V LVTTL /
3.3 V LVCMOS
8
8 mA High
35
0.60
4.57 0.04 1.13 1.52 0.43 4.64 3.92 2.60 3.14
3.3 V LVCMOS
Wide Range
100 A 8 mA High
35
0.60
6.78 0.04 1.57 2.18 0.43 6.78 5.72 3.72 4.35
2.5 V LVCMOS
8
8 mA High
35
0.60
4.94 0.04 1.43 1.63 0.43 4.71 4.94 2.60 2.98
1.8 V LVCMOS
4
4 mA High
35
0.60
6.53 0.04 1.35 1.90 0.43 5.53 6.53 2.62 2.89
1.5 V LVCMOS
2
2 mA High
35
0.60
7.86 0.04 1.56 2.14 0.43 6.45 7.86 2.66 2.83
Notes:
1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ±100 A. Drive
strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models.
2. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range, as specified in the JESD8-B specification.
3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values.
Table 2-19 Summary of I/O Timing Characteristics—Software Default Settings (at 10 pF)
STD Speed Grade, Commercial-Case Conditions: TJ = 70°C, Worst Case VCC = 1.425 V
For A3PN020, A3PN015, and A3PN010
I/O Standard
Drive
S
trength
(mA)
E
qui
va
le
n
tSo
ft
w
a
re
De
fa
ult
Drive
S
trength
Option
1
Sl
ew
Rat
e
Cap
a
citive
L
o
a
d
(pF
)
t DO
UT
(ns)
t DP
(ns)
t DI
N
(ns)
t PY
(ns)
t PYS
(ns)
t EO
U
T
(ns)
t ZL
(ns)
t ZH
(ns)
t LZ
(ns)
t HZ
(ns)
3.3 V LVTTL /
3.3 V LVCMOS
8
8 mA
High
10
0.60 2.73 0.04 1.13 1.52 0.43 2.77 2.23 2.60 3.14
3.3 V LVCMOS
Wide Range
100 A 8 mA
High
10
0.603.940.041.572.180.433.943.163.724.35
2.5 V LVCMOS
8
8 mA
High
10
0.60 2.76 0.04 1.43 1.63 0.43 2.80 2.60 2.60 2.98
1.8 V LVCMOS
4
4 mA
High
10
0.60 3.22 0.04 1.35 1.90 0.43 3.24 3.22 2.62 2.89
1.5 V LVCMOS
2
2 mA
High
10
0.60 3.76 0.04 1.56 2.14 0.43 3.74 3.76 2.66 2.83
Notes:
1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ±100 A. Drive
strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models.
2. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range, as specified in the JESD8-B specification.
3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values.
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