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參數(shù)資料
| 型號(hào)： | A42MX16-1CQ100I |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | IC LI-ION BATT CHARGER 10-MLP |
| 中文描述： | 40MX和42MX FPGA系列 |
| 文件頁數(shù)： | 70/120頁 |
| 文件大?。?/td> | 854K |
| 代理商： | A42MX16-1CQ100I |
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53
4958B–AUTO–11/10
Atmel ATA6285/ATA6286 [Preliminary]
Bit 0 - PCIF0: Pin Change Interrupt Flag 0
When a logic change on any PCINT7..0 pin triggers an interrupt request, PCIF0 becomes set
(one). If the I-bit in SREG and the PCIE0 bit in PCICR are set (one), the MCU will jump to the
corresponding Interrupt Vector. The flag is cleared when the interrupt routine is executed. Alter-
natively, the flag can be cleared by writing a logical one to it.
3.11.6
Pin Change Mask Register 0 – PCMSK0
Bit 7..0 - PCINT7..0: Pin Change INTerrupt enable mask 7..0
Each PCINT7..0 bit selects whether pin change interrupt is enabled on the corresponding I/O
pin. If PCINT7..0 is set and the PCIE0 bit in PCICR is set, pin change interrupt is enabled on the
corresponding I/O pin. If PCINT7..0 is cleared, pin change interrupt on the corresponding I/O pin
is disabled.
3.11.7
Pin Change Mask Register 1 – PCMSK1
Bits 7..3 - Res: Reserved Bits
These bits are reserved bits at the ATA6289 and will always read as zero.
Bit 2..0 - PCINT10..8: Pin Change INTerrupt enable mask 10..8
Each PCINT10..8-bit selects whether pin change interrupt is enabled on the corresponding I/O
pin. If PCINT10..8 is set and the PCIE1 bit in PCICR is set, pin change interrupt is enabled on
the corresponding I/O pin. If PCINT10..8 is cleared, pin change interrupt on the corresponding
I/O pin is disabled.
3.11.8
Pin Change Mask Register 2 – PCMSK2
Bit 7..0 - PCINT23..16: Pin Change INTerrupt enable mask 23..16
Each PCINT23..16-bit selects whether pin change interrupt is enabled on the corresponding I/O
pin. If PCINT23..16 is set and the PCIE2 bit in PCICR is set, pin change interrupt is enabled on
the corresponding I/O pin. If PCINT23..16 is cleared, pin change interrupt on the corresponding
I/O pin is disabled.
Bit
7
6
5
432
10
PCINT7 PCINT6 PCINT5 PCINT4 PCINT3 PCINT2 PCINT1 PCINT0
PCMSK0
Read/Write
R/W
Initial Value
0
000
00
Bit
765
43
2
1
0
-
PCINT10 PCINT9 PCINT8 PCMSK1
Read/Write
RR
RRR
R/W
Initial Value
000
00
0
Bit
7
6
5
432
1
0
PCINT23 PCINT22 PCINT21 PCINT20 PCINT19 PCINT18 PCINT17 PCINT16 PCMSK2
Read/Write
R/W
Initial Value
0
000
0
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| A42MX16-1CQ100M | IC I2C PROG PENTA ULDO 20-MLP |
| A42MX16-1PL100 | 40MX and 42MX FPGA Families |
| A42MX16-1PL100A | IC TVS BI-DIR 5V 350W SOD-323 |
| A42MX16-1PL100B | 40MX and 42MX FPGA Families |
| A42MX16-1PL100ES | 40MX and 42MX FPGA Families |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| A42MX16-1CQ100M | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:40MX and 42MX FPGA Families |
| A42MX16-1PL100 | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:40MX and 42MX FPGA Families |
| A42MX16-1PL100A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families |
| A42MX16-1PL100B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families |
| A42MX16-1PL100ES | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:40MX and 42MX FPGA Families |
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