參數(shù)資料
型號: A42MX16-2VQ100ES
廠商: Electronic Theatre Controls, Inc.
英文描述: 40MX and 42MX FPGA Families
中文描述: 40MX和42MX FPGA系列
文件頁數(shù): 13/120頁
文件大小: 854K
代理商: A42MX16-2VQ100ES
11
4958B–AUTO–11/10
Atmel ATA6285/ATA6286 [Preliminary]
3.5
Atmel AVR CPU Core
3.5.1
Architectural Overview
Figure 3-2.
Block Diagram of the Atmel
AVR Architecture
In order to maximize performance and parallelism, the Atmel AVR uses Harvard architecture -
with separate memories and buses for program and data. Instructions in the program memory
are executed with a single level pipelining. While one instruction is being executed, the next
instruction is pre-fetched from the program memory. This concept enables instructions to be
executed in every clock cycle. The program memory is In- System Reprogrammable Flash
memory.
The fast-access Register File contains 32 x 8-bit general purpose working registers with a single
clock cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation. In a typ-
ical ALU operation, two operands are output from the Register File, the operation is executed,
and the result is stored back in the Register File - in one clock cycle.
Status and
Control
32 x 8
General
Purpose
Registers
ALU
Data
SRAM
Program
Counter
Flash
Program
Memory
Instruction
Register
Instruction
Decoder
Control
Lines
EEPROM
I/O Lines
Di
rect
Ad
d
re
ss
ing
Indir
e
c
tA
ddr
e
ss
ing
Interrupt
Unit
SPI
Unit
Watchdog
Tim e r
Clock
Management
LF-
Receiver
I/O Module 1
I/O Module n
Data Bus 8-bit
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