參數(shù)資料
型號(hào): A42MX16-2VQ100ES
廠商: Electronic Theatre Controls, Inc.
英文描述: 40MX and 42MX FPGA Families
中文描述: 40MX和42MX FPGA系列
文件頁數(shù): 96/120頁
文件大?。?/td> 854K
代理商: A42MX16-2VQ100ES
77
4958B–AUTO–11/10
Atmel ATA6285/ATA6286 [Preliminary]
Bits 2..0 - WDPS2..0: WatchDog Prescaler Select Bits 2 - 0
The WDPS2, WDPS1, and WDPS0 bits determine the Watchdog Timer prescaling clock output
(CLK
WD) when the Watchdog Timer is enabled. The different prescaling values and their corre-
sponding Timeout periods are shown in Table 3-31.
3.13.3.2
Timer0 Control Register – T0CR
Bits 7 to 5 – T0PBS2..0: Timer0 Prescaler B Select Bits 2 to 0
The T0PBS2, T0PBS1, and T0PBS0 bits determine the Timer0 prescaling clock output
(CLK
SEN) and additionally the mode of the motion sensor. The different prescaling values and
their corresponding time-out periods are shown in Table 3-32.
Table 3-31.
Watchdog Timer Prescaler Select Bit Description
WDPS2 WDPS1 WDPS0
Number of Oscillator
Cycles (SCL)
Total Numbers of WDT
Cycles
8
× SCL = WDT
Typical Time-out
at VCC = 3V/25°C
and
T
SCL = 1 / 90kHz
0
1K cycles
8
× 1K = 8K cycles
90 ms
0
1
2K cycles
8
× 2K = 16K cycles
180 ms
0
1
0
4K cycles
8
× 4K = 32K cycles
365 ms
0
1
8K cycles
8
× 8K = 64K cycles
730 ms
1
0
32K cycles
8
× 32K = 256K cycles
2.9s
1
0
1
64K cycles
8
× 64K = 512K cycles
5.8s
1
0
256K cycles
8
× 256K = 1024K cycles
23s
1
512K cycles
8
× 512K = 4096K cycles
47s
Bit
76
5432
10
T0PBS2 T0PBS1 T0PBS0
T0PR
T0IE
T0PAS2 T0PAS1 T0PAS0
T0CR
Read/Write
R/WR/W
Initial Value
00
0000
00
Table 3-32.
Timer0 Prescaler B Select Bit Description
T0PBS2 T0PBS1 T0PBS0
Motion Sensor
Mode
Number of Oscillator Cycles
(SCL)
Typical Time-out at
VCC = 3V/25°C and
TSCL ≈ 1 / 90kHz for
CLK
SEN
0
Disabled
None
Disabled
0
1
Running
32K cycles
0.365s
0
1
0
Running
64K cycles
0.730s
0
1
Running
128K cycles
1.46s
1
0
Running
256K cycles
2.9s
1
0
1
Running
512K cycles
5.8s
1
0
Running
32cycles (used for test)
Reserved (355s)
1
Disabled
Reserved
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