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參數(shù)資料
| 型號： | A42MX24-2VQ100A |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 40MX and 42MX FPGA Families |
| 中文描述： | 40MX和42MX FPGA系列 |
| 文件頁數(shù)： | 19/93頁 |
| 文件大?。?/td> | 854K |
| 代理商： | A42MX24-2VQ100A |
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26
Data Device Corporation
www.ddc-web.com
BU-6474X/6484X/6486X
J-07/05-0
REMOTE TERMINAL (RT) ARCHITECTURE
The Mini-ACE Mark3's RT architecture builds upon that of the
ACE and Mini-ACE. The Mini-ACE Mark3 provides multiprotocol
support, with full compliance to all of the commonly used data bus
standards, including MIL-STD-1553A, MIL-STD-1553B Notice 2,
STANAG 3838, General Dynamics 16PP303, and McAir A3818,
A5232, and A5690. For the Mini-ACE Mark3 RT mode, there is
programmable flexibility enabling the RT to be configured to fulfill
any set of system requirements. This includes the capability to
meet the MIL-STD-1553A response time requirement of 2 to 5 s,
and multiple options for mode code subaddresses, mode codes,
RT status word, and RT BIT word.
The Mini-ACE Mark3 RT protocol design implements all of the
MIL-STD-1553B message formats and dual redundant mode
codes. The design has passed validation testing for MIL-STD-
1553B compliance. The Mini-ACE Mark3 RT performs compre-
hensive error checking including word and format validation, and
checks for various RT-to-RT transfer errors. One of the main fea-
tures of the Mini-ACE Mark3 RT is its choice of memory man-
agement options. These include single buffering by subaddress,
double buffering for individual receive subaddresses, circular
buffering by individual subaddresses, and global circular buffering
for multiple (or all) subaddresses.
Other features of the Mini-ACE Mark3 RT include a set of inter-
rupt conditions, a flexible status queue with filtering based on
valid and/or invalid messages, flexible command illegalization,
programmable busy by subaddress, multiple options on time tag-
ging, and an "auto-boot" feature which allows the RT to initialize
as an online RT with the busy bit set following power turn-on.
RT MEMORY ORGANIZATION
TABLE 38 illustrates a typical memory map for an Mini-ACE
Mark3 RT with 4K RAM. The two Stack Pointers reside in fixed
locations in the shared RAM address space: address 0100 (hex)
for the Area A Stack Pointer and address 0104 for the Area B
Stack Pointer. In addition to the Stack Pointer, there are several
other areas of the shared RAM address space that are designat-
ed as fixed locations (all shown in bold). These are for the Area
A and Area B lookup tables, the illegalization lookup table, the
busy lookup table, and the mode code data tables.
The RT lookup tables (reference TABLE 39) provide a mecha-
nism for allocating data blocks for individual transmit, receive, or
broadcast subaddresses. The RT lookup tables include subad-
dress control words as well as the individual data block pointers.
If command illegalization is used, address range 0300-03FF is
used for command illegalizing. The descriptor stack RAM area, as
well as the individual data blocks, may be located in any of the
non-fixed areas in the shared RAM address space.
Note that in TABLE 38, there is no area allocated for "Stack B".
This is shown for purpose of simplicity of illustration. Also, note
that in TABLE 38, the allocated area for the RT command stack is
256 words. However, larger stack sizes are possible. That is, the
RT command stack size may be programmed for 256 words (64
messages), 512, 1024, or 2048 words (512 messages) by means
of bits 14 and 13 of Configuration Register 3.
Data Block 100
0FE0-0FFF
Data Block 6
0420-043F
Data Block 5
0400-041F
Command Illegalizing Table
0300-03FF
RESERVED
Data Block 1-4
0280-02FF
Data Block 0
0260-027F
(not used)
0248-025F
Busy Bit Lookup Table
0240-0247
Lookup Table B
01C0-023F
Lookup Table A
0140-01BF
Mode Code Data
0110-013F
Mode Code Selective Interrupt Table
0108-010F
Global Circular Buffer B Pointer
Stack Pointer B
0105
0104
RESERVED
0102-0103
Global Circular Buffer A Pointer
Stack Pointer A
0101
0100
Stack A
0000-00FF
DESCRIPTION
ADDRESS
(HEX)
0106-0107
TABLE 38. TYPICAL RT MEMORY MAP (SHOWN
FOR 4K RAM)
Subaddress
Control Word
Lookup Table
(Optional)
SACW SA0
SACW SA31
0220
023F
01A0
01BF
Broadcast
Lookup Pointer
Table
(Optional)
Bcst SA0
Bcst SA31
0200
021F
0180
019F
Transmit
Lookup Pointer
Table
Tx SA0
Tx SA31
01E0
01FF
0160
017F
Receive
(/Broadcast)
Lookup Pointer
Table
Rx(/Bcst) SA0
Rx(/Bcst) SA31
01C0
01DF
0140
015F
COMMENT
DESCRIPTION
AREA B
AREA A
TABLE 39. RT LOOK-UP TABLES
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| A42MX24-2VQ100B | 40MX and 42MX FPGA Families |
| A42MX24-3PQ100B | 40MX and 42MX FPGA Families |
| A42MX24-3BG100 | 40MX and 42MX FPGA Families |
| A42MX24-3PL100 | 40MX and 42MX FPGA Families |
| A42MX24-3PL100A | 40MX and 42MX FPGA Families |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| A42MX24-3PL84 | 功能描述:IC FPGA MX SGL CHIP 36K 84-PLCC RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:MX 產(chǎn)品培訓(xùn)模塊:Three Reasons to Use FPGA's in Industrial Designs Cyclone IV FPGA Family Overview 特色產(chǎn)品:Cyclone? IV FPGAs 標(biāo)準(zhǔn)包裝:60 系列:CYCLONE® IV GX LAB/CLB數(shù):9360 邏輯元件/單元數(shù):149760 RAM 位總計(jì):6635520 輸入/輸出數(shù):270 門數(shù):- 電源電壓:1.16 V ~ 1.24 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:484-BGA 供應(yīng)商設(shè)備封裝:484-FBGA（23x23） |
| A42MX24-3PL84I | 功能描述:IC FPGA MX SGL CHIP 36K 84-PLCC RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:MX 產(chǎn)品培訓(xùn)模塊:Three Reasons to Use FPGA's in Industrial Designs Cyclone IV FPGA Family Overview 特色產(chǎn)品:Cyclone? IV FPGAs 標(biāo)準(zhǔn)包裝:60 系列:CYCLONE® IV GX LAB/CLB數(shù):9360 邏輯元件/單元數(shù):149760 RAM 位總計(jì):6635520 輸入/輸出數(shù):270 門數(shù):- 電源電壓:1.16 V ~ 1.24 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:484-BGA 供應(yīng)商設(shè)備封裝:484-FBGA（23x23） |
| A42MX24-3PLG84 | 功能描述:IC FPGA MX SGL CHIP 36K 84-PLCC RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:MX 產(chǎn)品培訓(xùn)模塊:Three Reasons to Use FPGA's in Industrial Designs Cyclone IV FPGA Family Overview 特色產(chǎn)品:Cyclone? IV FPGAs 標(biāo)準(zhǔn)包裝:60 系列:CYCLONE® IV GX LAB/CLB數(shù):9360 邏輯元件/單元數(shù):149760 RAM 位總計(jì):6635520 輸入/輸出數(shù):270 門數(shù):- 電源電壓:1.16 V ~ 1.24 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:484-BGA 供應(yīng)商設(shè)備封裝:484-FBGA（23x23） |
| A42MX24-3PLG84I | 功能描述:IC FPGA MX SGL CHIP 36K 84-PLCC RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:MX 產(chǎn)品培訓(xùn)模塊:Three Reasons to Use FPGA's in Industrial Designs Cyclone IV FPGA Family Overview 特色產(chǎn)品:Cyclone? IV FPGAs 標(biāo)準(zhǔn)包裝:60 系列:CYCLONE® IV GX LAB/CLB數(shù):9360 邏輯元件/單元數(shù):149760 RAM 位總計(jì):6635520 輸入/輸出數(shù):270 門數(shù):- 電源電壓:1.16 V ~ 1.24 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:484-BGA 供應(yīng)商設(shè)備封裝:484-FBGA（23x23） |
| A42MX24-3PQ160 | 功能描述:IC FPGA MX SGL CHIP 36K 160-PQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:MX 產(chǎn)品培訓(xùn)模塊:Three Reasons to Use FPGA's in Industrial Designs Cyclone IV FPGA Family Overview 特色產(chǎn)品:Cyclone? IV FPGAs 標(biāo)準(zhǔn)包裝:60 系列:CYCLONE® IV GX LAB/CLB數(shù):9360 邏輯元件/單元數(shù):149760 RAM 位總計(jì):6635520 輸入/輸出數(shù):270 門數(shù):- 電源電壓:1.16 V ~ 1.24 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:484-BGA 供應(yīng)商設(shè)備封裝:484-FBGA（23x23） |
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