參數(shù)資料
型號： A42MX24-2VQ100A
廠商： Electronic Theatre Controls, Inc.
英文描述： 40MX and 42MX FPGA Families
中文描述： 40MX和42MX FPGA系列
文件頁數(shù)： 36/93頁
文件大?。?/td> 854K
代理商： A42MX24-2VQ100A
41
Data Device Corporation
www.ddc-web.com
BU-6474X/6484X/6486X
J-07/05-0
2, 6
3, 4, 5, 7
6
2
2, 6
7, 8
6, 9
3, 4, 5, 7
6
6, 9
7, 8, 9
3, 4, 5, 7
6
3, 4, 5, 7
2, 6
MAX
TYP
MIN
UNITS
MAX
TYP
MIN
DESCRIPTION
REF
7.2
155
820
970
138
635
4.6
6.0
35
27
62
45
61
44
40
0
40
0
40
∞
40
0
25
520
35
165
150
135
265
250
235
205
187.5
170
30
23
11
315
300
285
30
15
40
12
16
10
3.6
105
15
NOTES
2, 9
2, 6
117
s
7.2
(contended access, with ENHANCED CPU ACCESS = “0” @ 10 MHz)
ns
150
(uncontended access @ 10 MHz)
ns
815
(contended access, with ENHANCED CPU ACCESS = “1” @ 12 MHz)
ns
965
(contended access, with ENHANCED CPU ACCESS = “1” @ 10 MHz)
ns
133
(uncontended access @ 12 MHz)
ns
630
(contended access, with ENHANCED CPU ACCESS = “1” s @ 16 MHz)
s
4.6
(contended access, with ENHANCED CPU ACCESS = “0” @ 16 MHz)
s
6.0
(contended access, with ENHANCED CPU ACCESS = “0” @ 12 MHz)
ns
40
@ 10 MHz
t3
t4
ns
32
@ 12 MHz
ns
67
@ 10 MHz
ns
50
@ 12 MHz
ns
71
@ 10 MHz
ns
54
@ 12 MHz
ns
40
CLOCK IN rising edge delay to output data valid
t19
ns
0
STRBD high hold time from READYD rising
t18
ns
40
STRBD rising delay to output data tri-state
t17
ns
0
Output Data hold time following STRBD rising edge
t16
ns
30
STRBD rising edge delay to IOEN rising edge and READYD rising edge
t15
ns
∞
READYD falling to STRBD rising release time
t14
ns
40
CLOCK IN rising edge delay to READYD falling
t13
t12
ns
0
SELECT hold time following IOEN falling
t6
ns
30
@ 16 MHz
ns
515
(contended access, with ENHANCED CPU ACCESS = “1” @ 20 MHz)
ns
30
Address valid setup time prior to CLOCK IN rising edge
t9
ns
165
150
135
IOEN falling delay to READYD falling (@ 20 MHz)
ns
265
250
235
@ 12 MHz
ns
205
187.5
170
@ 16 MHz
ns
30
MEM/REG, RD/WR hold time following CLOCK IN falling edge
t8
ns
33
@ 16 MHz
ns
21
Output Data valid prior to READYD falling (@ 20 MHz)
ns
315
300
285
@ 10 MHz
ns
30
Address hold time following CLOCK IN rising edge
t10
t11
ns
10
MEM/REG, RD/WR setup time prior to CLOCK IN falling edge
t7
ns
40
CLOCK IN rising edge delay to IOEN falling edge
t5
ns
17
Time for Address to become valid following SELECT and STRBD low (@ 20 MHz)
ns
21
@ 16 MHz
ns
15
Time for MEM/REG and RD/WR to become valid following SELECT and STRBD
low (@ 20 MHz)
s
3.6
(contended access, with ENHANCED CPU ACCESS = “0” @ 20 MHz)
ns
100
SELECT and STRBD low to IOEN low (uncontended access @ 20 MHz)
t2
ns
10
SELECT and STRBD low setup time prior to clock rising edge
t1
3.3V LOGIC
5V LOGIC
TABLE FOR FIGURE 13. CPU READING RAM OR REGISTERS
(SHOWN FOR 16-BIT, BUFFERED, NONZERO WAIT MODE)
ns
112
(uncontended access @ 16 MHz)
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