參數(shù)資料
型號： A42MX24-2VQ100A
廠商： Electronic Theatre Controls, Inc.
英文描述： 40MX and 42MX FPGA Families
中文描述： 40MX和42MX FPGA系列
文件頁數(shù)： 55/93頁
文件大?。?/td> 854K
代理商： A42MX24-2VQ100A
59
Data Device Corporation
www.ddc-web.com
BU-6474X/6484X/6486X
J-07/05-0
These two signals MUST be separated for "Transceiverless" operation.
Digital manchester biphase transmit data outputs. Connect directly to
corresponding inputs of a MIL-STD-1553 or MIL-STD-1773 (fiber
optic) transceiver.
TXDATA_IN_B
These two signals
MUST be directly
connected for normal
"Built-In" transceiver
operation.
R10
L7
TXDATA_OUT_B
P10
L8
These two signals MUST be separated for "Transceiverless" operation.
Digital manchester biphase transmit data outputs. Connect directly to
corresponding inputs of a MIL-STD-1553 or MIL-STD-1773 (fiber
optic) transceiver.
TXDATA_IN_B
These two signals
MUST be directly
connected for normal
"Built-In" transceiver
operation.
N12
M7
TXDATA_OUT_B
M12
M8
These two signals MUST be separated for "Transceiverless" operation.
Digital manchester biphase receive data inputs. Connect directly to
corresponding outputs of a MIL-STD-1553 or MIL-STD-1773 (fiber
optic) transceiver.
RXDATA_IN_B
These two signals
MUST be directly
connected for normal
"Built-In" transceiver
operation.
M13
P10
RXDATA_OUT_B
M14
P9
These two signals MUST be separated for "Transceiverless" operation.
Digital manchester biphase receive data inputs. Connect directly to
corresponding outputs of a MIL-STD-1553 or MIL-STD-1773 (fiber
optic) transceiver.
RXDATA_IN_B
These two signals
MUST be directly
connected for normal
"Built-In" transceiver
operation.
N13
R10
RXDATA_OUT_B
N14
R9
TABLE 59. MANDATORY ADDITIONAL CONNECTIONS & INTERFACE TO EXTERNAL TRANSCEIVER (CONT.)
SIGNAL NAME
FOR USE WITH EXTERNAL TRANSCEIVERS
"TRANSCEIVERLESS"
UTILIZING INTERNAL
"BUILT-IN"
TRANSCEIVERS
BU-64840B3
BU-64860B3
BU-64743B8
BU-64843B8
BU-64863B8
BALL
D15 (MSB)
D15
16-bit bi-directional data bus. This bus interfaces the host processor to the Mini-
ACE Mark3's internal registers and internal RAM. In addition, in transparent mode,
this bus allows data transfers to take place between the internal protocol/memory
management logic and up to 64K x 16 of external RAM. Most of the time, the out-
puts for D15 through D0 are in the high impedance state. They drive outward in
the buffered or transparent mode when the host CPU reads the internal RAM or
registers.
Also, in the transparent mode, D15-D0 will drive outward (towards the host) when
the protocol/management logic is accessing (either reading or writing) internal
RAM, or writing to external RAM. In the transparent mode, D15-D0 drives inward
when the CPU writes internal registers or RAM, or when the protocol/memory
management logic reads external RAM.
D14
E17
D13
E16
D12
E18
TABLE 60. DATA BUS
SIGNAL NAME
DESCRIPTION
BU-64840B3
BU-64860B3
BALL
D16
F15
E16
F18
D11
E15
D10
F16
D09
F15
D08
F18
E17
E18
F16
G18
D07
F17
D06
G18
D05
G16
D04
G17
F17
J18
H17
H18
D03
G15
D02
H18
D01
J17
D00 (LSB)
H17
G17
J17
K16
K17
BU-64743B8
BU-64843B8
BU-64863B8
BALL
BALL GRID ARRAY PACKAGE - SIGNAL DESCRIPTIONS BY FUNCTIONAL GROUPS (CONT.)
相關(guān)PDF資料
PDF描述
A42MX24-2VQ100B 40MX and 42MX FPGA Families
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A42MX24-3BG100 40MX and 42MX FPGA Families
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A42MX24-3PL100A 40MX and 42MX FPGA Families
相關(guān)代理商/技術(shù)參數(shù)
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A42MX24-3PL84 功能描述:IC FPGA MX SGL CHIP 36K 84-PLCC RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:MX 產(chǎn)品培訓(xùn)模塊:Three Reasons to Use FPGA's in Industrial Designs Cyclone IV FPGA Family Overview 特色產(chǎn)品:Cyclone? IV FPGAs 標(biāo)準(zhǔn)包裝:60 系列:CYCLONE® IV GX LAB/CLB數(shù):9360 邏輯元件/單元數(shù):149760 RAM 位總計(jì):6635520 輸入/輸出數(shù):270 門數(shù):- 電源電壓:1.16 V ~ 1.24 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:484-BGA 供應(yīng)商設(shè)備封裝:484-FBGA（23x23）
A42MX24-3PL84I 功能描述:IC FPGA MX SGL CHIP 36K 84-PLCC RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:MX 產(chǎn)品培訓(xùn)模塊:Three Reasons to Use FPGA's in Industrial Designs Cyclone IV FPGA Family Overview 特色產(chǎn)品:Cyclone? IV FPGAs 標(biāo)準(zhǔn)包裝:60 系列:CYCLONE® IV GX LAB/CLB數(shù):9360 邏輯元件/單元數(shù):149760 RAM 位總計(jì):6635520 輸入/輸出數(shù):270 門數(shù):- 電源電壓:1.16 V ~ 1.24 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:484-BGA 供應(yīng)商設(shè)備封裝:484-FBGA（23x23）
A42MX24-3PLG84 功能描述:IC FPGA MX SGL CHIP 36K 84-PLCC RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:MX 產(chǎn)品培訓(xùn)模塊:Three Reasons to Use FPGA's in Industrial Designs Cyclone IV FPGA Family Overview 特色產(chǎn)品:Cyclone? IV FPGAs 標(biāo)準(zhǔn)包裝:60 系列:CYCLONE® IV GX LAB/CLB數(shù):9360 邏輯元件/單元數(shù):149760 RAM 位總計(jì):6635520 輸入/輸出數(shù):270 門數(shù):- 電源電壓:1.16 V ~ 1.24 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:484-BGA 供應(yīng)商設(shè)備封裝:484-FBGA（23x23）
A42MX24-3PLG84I 功能描述:IC FPGA MX SGL CHIP 36K 84-PLCC RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:MX 產(chǎn)品培訓(xùn)模塊:Three Reasons to Use FPGA's in Industrial Designs Cyclone IV FPGA Family Overview 特色產(chǎn)品:Cyclone? IV FPGAs 標(biāo)準(zhǔn)包裝:60 系列:CYCLONE® IV GX LAB/CLB數(shù):9360 邏輯元件/單元數(shù):149760 RAM 位總計(jì):6635520 輸入/輸出數(shù):270 門數(shù):- 電源電壓:1.16 V ~ 1.24 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:484-BGA 供應(yīng)商設(shè)備封裝:484-FBGA（23x23）
A42MX24-3PQ160 功能描述:IC FPGA MX SGL CHIP 36K 160-PQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:MX 產(chǎn)品培訓(xùn)模塊:Three Reasons to Use FPGA's in Industrial Designs Cyclone IV FPGA Family Overview 特色產(chǎn)品:Cyclone? IV FPGAs 標(biāo)準(zhǔn)包裝:60 系列:CYCLONE® IV GX LAB/CLB數(shù):9360 邏輯元件/單元數(shù):149760 RAM 位總計(jì):6635520 輸入/輸出數(shù):270 門數(shù):- 電源電壓:1.16 V ~ 1.24 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:484-BGA 供應(yīng)商設(shè)備封裝:484-FBGA（23x23）
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