參數(shù)資料
型號(hào)： A42MX24-3PL100
廠商： Electronic Theatre Controls, Inc.
英文描述： 40MX and 42MX FPGA Families
中文描述： 40MX和42MX FPGA系列
文件頁(yè)數(shù)： 26/93頁(yè)
文件大小： 854K
代理商： A42MX24-3PL100
32
Data Device Corporation
www.ddc-web.com
BU-6474X/6484X/6486X
J-07/05-0
TABLE 41. ILLEGALIZATION TABLE MEMORY MAP
3FC
3BE
37D
3C2
381
33F
300
ADDRESS
Own Addr / Tx, SA 30. WC15-0
Own Addr / Rx, SA 31. MC15-0
Brdcst / Tx, SA 30. WC31-16
Own Addr / Tx, SA 1. WC15-0
Own Addr / Rx, SA 0. MC31-16
Brdcst / Rx, SA 31. MC31-16
Brdcst / Rx, SA 0. MC15-0
DESCRIPTION
3FD
3BF
37E
3C3
382
340
301
Own Addr / Tx, SA 30. WC31-16
Own Addr / Rx, SA 31. MC31-16
Brdcst / Tx, SA 31. MC15-0
Own Addr / Tx, SA 1. WC31-16
Own Addr / Rx, SA 1. WC15-0
Brdcst / Tx, SA 0. MC15-0
Brdcst / Rx, SA 0. MC31-16
3FE
3C0
37F
383
341
302
Own Addr / Tx, SA 31. MC15-0
Own Addr / Tx, SA 0. MC15-0
Brdcst / Tx, SA 31. MC31-16
Own Addr / Rx, SA 1. WC31-16
Brdcst / Tx, SA 0. MC31-16
Brdcst / Rx, SA 1. WC15-0
3FF
3C1
380
342
303
Own Addr / Tx, SA 31. MC31-16
Own Addr / Tx, SA 0. MC31-16
Own Addr / Rx, SA 0. MC15-0
Brdcst / Tx, SA 1. WC15-0
Brdcst / Rx, SA 1. WC31-16
based interrupt events include End-of-Message, Selected mode
code, Format error, Subaddress control word interrupt, RT
Circular buffer Rollover, Handshake failure, RT Command stack
rollover,
transmitter
timeout,
MT
Data
Stack
rollover,
MT Command Stack rollover, RT Command Stack 50% rollover,
MT Data Stack 50% rollover, MT Command Stack 50% rollover,
and RT Circular buffer 50% rollover. Non-message interrupt
events/conditions include time tag rollover, RT address parity
error, RAM parity error, and BIT completed.
Bit 0 of the interrupt vector (interrupt status) word indicates
whether the entry is for a message interrupt event (if bit 0 is logic
"1") or a non-message interrupt event (if bit 0 is logic "0"). It is not
possible for one entry on the queue to indicate both a message
interrupt and a non-message interrupt.
As illustrated in FIGURE 10, for a message interrupt event, the
parameter word is a pointer. The pointer will reference the first
word of the RT or MT command stack descriptor (i.e., the Block
Status Word).
For a RAM Parity Error non-message interrupt, the parameter
will be the RAM address where the parity check failed. For the
RT address Parity Error, Protocol Self-test Complete, and Time
Tag rollover non-message interrupts, the parameter is not used;
it will have a value of 0000.
If enabled, an INTERRUPT STATUS QUEUE ROLLOVER inter-
rupt will be issued when the value of the queue pointer address
rolls over at a 64-word address boundary.
NOTE: Please see Appendix “F” of the Enhanced Mini-ACE
User’s Guide for important information applicable only to RT
MODE operation, enabling of the interrupt status queue and
use of specific non-message interrupts.
相關(guān)PDF資料
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A42MX24-3PL100A 40MX and 42MX FPGA Families
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A42MX24-3VQ100 40MX and 42MX FPGA Families
A42MX24-3VQ100A 40MX and 42MX FPGA Families
A42MX24-3VQ100B 40MX and 42MX FPGA Families
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