參數(shù)資料
型號(hào)： A42MX24-3PL100
廠商： Electronic Theatre Controls, Inc.
英文描述： 40MX and 42MX FPGA Families
中文描述： 40MX和42MX FPGA系列
文件頁(yè)數(shù)： 48/93頁(yè)
文件大?。?/td> 854K
代理商： A42MX24-3PL100
52
Data Device Corporation
www.ddc-web.com
BU-6474X/6484X/6486X
J-07/05-0
SELECT (I)
66
Device Select.
Generally connected to a CPU address decoder output to select the Mark3 for a transfer to/from either
RAM or register.
STRBD (I)
68
Strobe Data.
Used in conjunction with SELECT to initiate and control the data transfer cycle between the host processor
and the Mark3. STRBD must be asserted low through the full duration of the transfer cycle.
RD / WR (I)
71
Read/Write.
For host processor access, RD/WR selects between reading and writing. In the 16-bit buffered mode, if
POL_SEL is logic "0”, then RD/WR should be low (logic "0") for read accesses and high (logic "1") for write
accesses. If POL_SEL is logic "1", or the interface is configured for a mode other than 16-bit buffered
mode, then RD/WR is high (logic "1") for read accesses and low (logic "0") for write accesses.
ADDR_LAT(I) /
MEMOE (O)
20
Memory Output Enable or Address Latch.
In buffered mode, the ADDR_LAT input is used to configure the buffers for A15-A0, SELECT, MEM/REG,
and MSB/LSB (for 8-bit mode only) in latched mode (when low) or transparent mode (when high). That is,
the Mark3's internal transparent latches will track the values on A15-A0, SELECT, MEM/REG, and
MSB/LSB when ADDR_LAT is high, and latch the values when ADDR_LAT goes low.
In general, for interfacing to processors with a non-multiplexed address/data bus, ADDR_LAT should be
hardwired to logic "1". For interfacing to processors with a multiplexed address/data bus, ADDR_LAT
should be connected to a signal that indicates a valid address when ADDR_LAT is logic "1".
In transparent mode, MEMOE output signal is used to enable data outputs for external RAM read cycles
(normally connected to the OE input signal on external RAM chips).
ZEROWAIT (I) /
MEMWR (O)
28
Memory Write or Zero Wait.
In buffered mode, input signal (ZEROWAIT) used to select between the zero wait mode (ZEROWAIT = "0")
and the non-zero wait mode (ZEROWAIT = "1").
In transparent mode, active low output signal (MEMWR) asserted low during memory write transfers to
strobe data into external RAM (normally connected to the WR input signal on external RAM chips).
16 / 8 (I) /
DTREQ (O)
29
Data Transfer Request or Data Bus Select.
In buffered mode, input signal 16/8 used to select between the 16 bit data transfer mode (16/8= "1") and
the 8-bit data transfer mode (16/8 = "0").
In transparent mode (16-bit only), active low level output signal DTREQ used to request access to the
processor/RAM interface bus (address and data buses).
MSB / LSB (I) /
DTGRT (I)
72
Data Transfer Grant or Most Significant Byte/Least Significant Byte.
In 8-bit buffered mode, input signal (MSB/LSB) used to indicate which byte is currently being transferred
(MSB or LSB). The logic sense of MSB/LSB is controlled by the POL_SEL input. MSB/LSB is not used in
the 16-bit buffered mode.
In transparent mode, active low input signal (DTGRT) asserted in response to the DTREQ output to indi-
cate that control of the external processor/RAM bus has been transferred from the host processor to the
Mark3.
TABLE 53. PROCESSOR INTERFACE CONTROL
SIGNAL NAME
DESCRIPTION
BU-6474XF/GX
BU-6484XF/GX
BU-64863F/GX
PIN
FLAT PACK AND GULL WING PACKAGES - SIGNAL DESCRIPTIONS BY FUNCTIONAL GROUPS (CONT.)
相關(guān)PDF資料
PDF描述
A42MX24-3PL100A 40MX and 42MX FPGA Families
A42MX24-3PQ100A 40MX and 42MX FPGA Families
A42MX24-3VQ100 40MX and 42MX FPGA Families
A42MX24-3VQ100A 40MX and 42MX FPGA Families
A42MX24-3VQ100B 40MX and 42MX FPGA Families
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A42MX24-3PL84 功能描述:IC FPGA MX SGL CHIP 36K 84-PLCC RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門陣列） 系列:MX 產(chǎn)品培訓(xùn)模塊:Three Reasons to Use FPGA's in Industrial Designs Cyclone IV FPGA Family Overview 特色產(chǎn)品:Cyclone? IV FPGAs 標(biāo)準(zhǔn)包裝:60 系列:CYCLONE® IV GX LAB/CLB數(shù):9360 邏輯元件/單元數(shù):149760 RAM 位總計(jì):6635520 輸入/輸出數(shù):270 門數(shù):- 電源電壓:1.16 V ~ 1.24 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:484-BGA 供應(yīng)商設(shè)備封裝:484-FBGA（23x23）
A42MX24-3PL84I 功能描述:IC FPGA MX SGL CHIP 36K 84-PLCC RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門陣列） 系列:MX 產(chǎn)品培訓(xùn)模塊:Three Reasons to Use FPGA's in Industrial Designs Cyclone IV FPGA Family Overview 特色產(chǎn)品:Cyclone? IV FPGAs 標(biāo)準(zhǔn)包裝:60 系列:CYCLONE® IV GX LAB/CLB數(shù):9360 邏輯元件/單元數(shù):149760 RAM 位總計(jì):6635520 輸入/輸出數(shù):270 門數(shù):- 電源電壓:1.16 V ~ 1.24 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:484-BGA 供應(yīng)商設(shè)備封裝:484-FBGA（23x23）
A42MX24-3PLG84 功能描述:IC FPGA MX SGL CHIP 36K 84-PLCC RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門陣列） 系列:MX 產(chǎn)品培訓(xùn)模塊:Three Reasons to Use FPGA's in Industrial Designs Cyclone IV FPGA Family Overview 特色產(chǎn)品:Cyclone? IV FPGAs 標(biāo)準(zhǔn)包裝:60 系列:CYCLONE® IV GX LAB/CLB數(shù):9360 邏輯元件/單元數(shù):149760 RAM 位總計(jì):6635520 輸入/輸出數(shù):270 門數(shù):- 電源電壓:1.16 V ~ 1.24 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:484-BGA 供應(yīng)商設(shè)備封裝:484-FBGA（23x23）
A42MX24-3PLG84I 功能描述:IC FPGA MX SGL CHIP 36K 84-PLCC RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門陣列） 系列:MX 產(chǎn)品培訓(xùn)模塊:Three Reasons to Use FPGA's in Industrial Designs Cyclone IV FPGA Family Overview 特色產(chǎn)品:Cyclone? IV FPGAs 標(biāo)準(zhǔn)包裝:60 系列:CYCLONE® IV GX LAB/CLB數(shù):9360 邏輯元件/單元數(shù):149760 RAM 位總計(jì):6635520 輸入/輸出數(shù):270 門數(shù):- 電源電壓:1.16 V ~ 1.24 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:484-BGA 供應(yīng)商設(shè)備封裝:484-FBGA（23x23）
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