參數(shù)資料
型號: A42MX24-3PL84M
英文描述: Field Programmable Gate Array (FPGA)
中文描述: 現(xiàn)場可編程門陣列(FPGA)
文件頁數(shù): 20/116頁
文件大?。?/td> 3110K
代理商: A42MX24-3PL84M
40MX and 42MX FPGA Families
20
v5.0
Determining Average Switching Frequency
To determine the switching frequency for a design, the data
input values to the circuit must be clearly understood. The
following guidelines represent worst-case scenarios; these
can be used to generally predict the upper limits of power
dissipation.
Logic Modules (m)
=
80% of
Combinatorial
Modules
# of Inputs/4
# of Outputs/4
40% of Sequential
Modules
40% of Sequential
Modules
35 pF
Inputs Switching (n)
Outputs Switching (p)
First Routed Array Clock Loads
(q
1
)
Second Routed Array Clock
Loads (q
2
)
Load Capacitance (C
L
)
=
=
=
=
=
Average Logic Module Switching
Rate (f
m
)
Average Input Switching Rate
(f
n
)
Average Output Switching Rate
(f
p
)
Average First Routed Array
Clock Rate (f
q1
)
Average Second Routed Array
Clock Rate (f
q2
)
=
F/10
=
F/5
=
F/10
=
F
=
F/2
Logic Modules (m)
=
80% of
Combinatorial
Modules
40MX Timing Model*
* Values are shown for 40MX
‘–
3
speed devices at 5.0V worst-case commercial conditions.
Output Delay
Input Delay
I/O Module
t
INYL
= 0.62 nst
IRD2
= 2.59 ns
Logic Module
t
PD
= 1.24 ns
t
CO
= 1.24 ns
I/O Module
t
RD1
= 1.28 ns
t
RD2
= 1.80 ns
t
DLH
= 3.32 ns
Array
Clock
F
MAX
= 180 MHz
t
RD4
= 2.33 ns
t
RD8
= 4.93 ns
Predicted
Routing
Delays
t
CKH
= 4.55 ns
FO = 128
t
IRD1
= 2.09 ns
t
IRD4
= 3.64 ns
t
IRD8
= 5.73 ns
t
ENHZ
= 7.92 ns
Internal Delays
相關(guān)PDF資料
PDF描述
A42MX24-3PQ160 Field Programmable Gate Array (FPGA)
A42MX24-3PQ160I Field Programmable Gate Array (FPGA)
A42MX24-3PQ160M Field Programmable Gate Array (FPGA)
A42MX24-3PQ208 Field Programmable Gate Array (FPGA)
A42MX24-3PQ208I Field Programmable Gate Array (FPGA)
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