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參數(shù)資料
| 型號(hào)： | A42MX24-3PQ160 |
| 英文描述： | Field Programmable Gate Array (FPGA) |
| 中文描述： | 現(xiàn)場(chǎng)可編程門陣列（FPGA） |
| 文件頁(yè)數(shù)： | 80/116頁(yè) |
| 文件大?。?/td> | 3110K |
| 代理商： | A42MX24-3PQ160 |
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40MX and 42MX FPGA Families
80
v5.0
Pin Descriptions
CLK, CLKA,
CLKB
TTL clock inputs for clock distribution networks. The clock
input is buffered prior to clocking the logic modules. This
pin can also be used as an I/O.
Global Clock (Input)
DCLK
TTL clock input for diagnostic probe and device
programming. DCLK is active when the MODE pin is HIGH.
This pin functions as an I/O when the MODE pin is LOW.
Diagnostic Clock (Input)
GND
Input LOW supply voltage.
Ground (Input)
I/O
Input, output, tri-state, or bi-directional buffer. Input and
output levels are compatible with standard TTL and CMOS
specifications. Unused I/O pins are automatically driven
LOW by the Designer Series software.
Input/Output (Input, Output)
LP
Controls the low power mode of all 42MX devices. This pin
must be set HIGH to switch the device to low power mode.
To exit the LOW power mode, the LP pin must be set LOW.
Low Power Mode
MODE
Controls the use of multifunction pins (DCLK, PRA, PRB,
SDI, TDO). To provide verification capability, the MODE pin
should be held HIGH. To facilitate this, the MODE pin
should be terminated to GND through a 10K
resistor so
that the MODE pin can be pulled HIGH when required.
Mode (Input)
NC
This pin is not connected to circuitry within the device.
These pins can be driven to any voltage or can be left
floating with no effect on the operation of the device.
No Connection
PRA, I/O
The Probe A pin is used to output data from any
user-defined design node within the device. This
independent diagnostic pin can be used in conjunction with
the Probe B pin to allow real-time diagnostic output of any
signal path within the device. The Probe A pin can be used
as a user-defined I/O when verification has been completed.
The pin's probe capabilities can be permanently disabled to
protect programmed design confidentiality. PRA is
accessible when the MODE pin is HIGH. This pin functions
as an I/O when the MODE pin is LOW.
Probe A (Output)
PRB, I/O
The Probe B pin is used to output data from any
user-defined design node within the device. This
independent diagnostic pin can be used in conjunction with
the Probe A pin to allow real-time diagnostic output of any
signal path within the device. The Probe B pin can be used
as a user-defined I/O when verification has been completed.
The pin
’
s probe capabilities can be permanently disabled to
protect programmed design confidentiality. PRB is
Probe B (Output)
accessible when the MODE pin is HIGH. This pin functions
as an I/O when the MODE pin is LOW.
QCLKA,B,C,D Quadrant Clock (Input/Output)
Quadrant clock inputs. When not used as a register control
signal, these pins can function as general-purpose I/Os.
SDI
Serial data input for diagnostic probe and device
programming. SDI is active when the MODE pin is HIGH.
This pin functions as an I/O when the MODE pin is LOW.
Serial Data Input (Input)
SDO, TDO,
I/O
Serial data output for diagnostic probe and device
programming. SDO is active when the MODE pin is HIGH.
This pin functions as an I/O when the MODE pin is LOW.
SDO is not available for 40MX devices.
Serial Data (Output)
TCK
Clock signal to shift the Boundary Scan Test (BST) data into
the device. This pin functions as an I/O when the test fuse is
not programmed. BST pins are only available in the
A42MX24, A42MX24A, and A42MX36 devices.
Test Clock
TDI
Serial data input for BST instructions and data. Data is
shifted in on the rising edge of TCK. This pin functions as an
I/O when the test fuse is not programmed. BST pins are only
available in the A42MX24 and A42MX36 devices.
Test Data In
TDO
Serial data output for BST instructions and test data. This
pin functions as an I/O when the test fuse is not
programmed. BST pins are only available in the A42MX24
and A42MX36 devices.
Test Data Out
TMS
Serial data input for boundary scan test mode. Data is shifted
in on the rising edge of TCK. This pin functions as an I/O
when the test fuse is not programmed. BST pins are only
available in the A42MX24 and A42MX36 devices.
Test Mode Select
V
CC
Input HIGH supply voltage.
Supply Voltage (Input)
V
CCA
Input HIGH supply voltage, supplies array core only.
Supply Voltage (Input)
V
CCI
Input HIGH supply voltage, supplies I/O cells only.
Supply Voltage (Input)
WD
When a wide decode module is used in a 42MX device, this
pin can be used as a dedicated output from the wide decode
module. This direct connection eliminates additional
interconnect delays associated with regular logic modules.
To implement the direct I/O connection, connect an output
buffer of any type to the output of the wide decode macro
and place this output on one of the reserved WD pins.
Wide Decode Output
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| A42MX24-3PQ160I | Field Programmable Gate Array (FPGA) |
| A42MX24-3PQ160M | Field Programmable Gate Array (FPGA) |
| A42MX24-3PQ208 | Field Programmable Gate Array (FPGA) |
| A42MX24-3PQ208I | Field Programmable Gate Array (FPGA) |
| A42MX24-3PQ208M | Field Programmable Gate Array (FPGA) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| A42MX24-3PQ160I | 功能描述:IC FPGA MX SGL CHIP 36K 160-PQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門陣列） 系列:MX 產(chǎn)品培訓(xùn)模塊:Three Reasons to Use FPGA's in Industrial Designs Cyclone IV FPGA Family Overview 特色產(chǎn)品:Cyclone? IV FPGAs 標(biāo)準(zhǔn)包裝:60 系列:CYCLONE® IV GX LAB/CLB數(shù):9360 邏輯元件/單元數(shù):149760 RAM 位總計(jì):6635520 輸入/輸出數(shù):270 門數(shù):- 電源電壓:1.16 V ~ 1.24 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:484-BGA 供應(yīng)商設(shè)備封裝:484-FBGA（23x23） |
| A42MX24-3PQ208 | 功能描述:IC FPGA MX SGL CHIP 36K 208-PQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門陣列） 系列:MX 產(chǎn)品培訓(xùn)模塊:Three Reasons to Use FPGA's in Industrial Designs Cyclone IV FPGA Family Overview 特色產(chǎn)品:Cyclone? IV FPGAs 標(biāo)準(zhǔn)包裝:60 系列:CYCLONE® IV GX LAB/CLB數(shù):9360 邏輯元件/單元數(shù):149760 RAM 位總計(jì):6635520 輸入/輸出數(shù):270 門數(shù):- 電源電壓:1.16 V ~ 1.24 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:484-BGA 供應(yīng)商設(shè)備封裝:484-FBGA（23x23） |
| A42MX24-3PQ208I | 功能描述:IC FPGA MX SGL CHIP 36K 208-PQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門陣列） 系列:MX 產(chǎn)品培訓(xùn)模塊:Three Reasons to Use FPGA's in Industrial Designs Cyclone IV FPGA Family Overview 特色產(chǎn)品:Cyclone? IV FPGAs 標(biāo)準(zhǔn)包裝:60 系列:CYCLONE® IV GX LAB/CLB數(shù):9360 邏輯元件/單元數(shù):149760 RAM 位總計(jì):6635520 輸入/輸出數(shù):270 門數(shù):- 電源電壓:1.16 V ~ 1.24 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:484-BGA 供應(yīng)商設(shè)備封裝:484-FBGA（23x23） |
| A42MX24-3PQ208IPM79 | 制造商:Microsemi Corporation 功能描述:FPGA 36K GATES 912 CELLS 0.45UM 3.3V/5V 208PQFP - Trays |
| A42MX24-3PQG160 | 功能描述:IC FPGA MX SGL CHIP 36K 160-PQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門陣列） 系列:MX 產(chǎn)品培訓(xùn)模塊:Three Reasons to Use FPGA's in Industrial Designs Cyclone IV FPGA Family Overview 特色產(chǎn)品:Cyclone? IV FPGAs 標(biāo)準(zhǔn)包裝:60 系列:CYCLONE® IV GX LAB/CLB數(shù):9360 邏輯元件/單元數(shù):149760 RAM 位總計(jì):6635520 輸入/輸出數(shù):270 門數(shù):- 電源電壓:1.16 V ~ 1.24 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:484-BGA 供應(yīng)商設(shè)備封裝:484-FBGA（23x23） |
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