Table 2-8 AC Specifications (5 V PCI Operation) Symbol Parameter Condition Min. Max. Units I
參數(shù)資料
型號(hào)： A54SX08A-TQ144I
廠商： Microsemi SoC
文件頁(yè)數(shù)： 26/108頁(yè)
文件大?。?/td> 0K
描述： IC FPGA SX 12K GATES 144-TQFP
標(biāo)準(zhǔn)包裝： 60
系列： SX-A
LAB/CLB數(shù)： 768
輸入/輸出數(shù)： 113
門(mén)數(shù)： 12000
電源電壓： 2.25 V ~ 5.25 V
安裝類(lèi)型： 表面貼裝
工作溫度： -40°C ~ 85°C
封裝/外殼： 144-LQFP
供應(yīng)商設(shè)備封裝： 144-TQFP（20x20）
SX-A Family FPGAs
2- 4
v5.3
Table 2-8 AC Specifications (5 V PCI Operation)
Symbol
Parameter
Condition
Min.
Max.
Units
IOH(AC)
Switching Current High
0 < VOUT ≤ 1.4
1
–44
–
mA
1.4
≤ V
OUT < 2.4
1, 2
(–44 + (VOUT – 1.4)/0.024)
–
mA
3.1 < VOUT < VCCI
1, 3
–
–
(Test Point)
VOUT = 3.1
3
––142
mA
IOL(AC)
Switching Current Low
VOUT ≥ 2.2
1
95
–
mA
2.2 > VOUT > 0.55
1
(VOUT/0.023)
–
mA
0.71 > VOUT > 0
1, 3
–
–
(Test Point)
VOUT = 0.71
3
–
206
mA
ICL
Low Clamp Current
–5 < VIN ≤ –1
–25 + (VIN + 1)/0.015
–
mA
slewR
Output Rise Slew Rate
0.4 V to 2.4 V load 4
15
V/ns
slewF
Output Fall Slew Rate
2.4 V to 0.4 V load 4
15
V/ns
Notes:
1. Refer to the V/I curves in Figure 2-1 on page 2-5. Switching current characteristics for REQ# and GNT# are permitted to be one half
of that specified here; i.e., half size output drivers may be used on these signals. This specification does not apply to CLK and RST#,
which are system outputs. “Switching Current High” specifications are not relevant to SERR#, INTA#, INTB#, INTC#, and INTD#,
which are open drain outputs.
2. Note that this segment of the minimum current curve is drawn from the AC drive point directly to the DC drive point rather than
toward the voltage rail (as is done in the pull-down curve). This difference is intended to allow for an optional N-channel pull-up.
3. Maximum current requirements must be met as drivers pull beyond the last step voltage. Equations defining these maximums (A
and B) are provided with the respective diagrams in Figure 2-1 on page 2-5. The equation defined maximum should be met by
design. In order to facilitate component testing, a maximum current test point is defined for each side of the output driver.
4. This parameter is to be interpreted as the cumulative edge rate across the specified range, rather than the instantaneous rate at any
point within the transition range. The specified load (diagram below) is optional; i.e., the designer may elect to meet this parameter
with an unloaded output per revision 2.0 of the PCI Local Bus Specification. However, adherence to both maximum and minimum
parameters is now required (the maximum is no longer simply a guideline). Since adherence to the maximum slew rate was not
required prior to revision 2.1 of the specification, there may be components in the market for some time that have faster edge
rates; therefore, motherboard designers must bear in mind that rise and fall times faster than this specification could occur and
should ensure that signal integrity modeling accounts for this. Rise slew rate does not apply to open drain outputs.
Output
Buffer
1/2 in. max.
50 pF
Pin
相關(guān)PDF資料
PDF描述
A54SX08A-1TQ144 IC FPGA SX 12K GATES 144-TQFP
HSM44DRYS CONN EDGECARD 88POS DIP .156 SLD
A54SX08A-TQG144I IC FPGA SX 12K GATES 144-TQFP
A54SX08A-1TQG144 IC FPGA SX 12K GATES 144-TQFP
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