參數(shù)資料
型號: A54SX08A-TQG144I
廠商: Microsemi SoC
文件頁數(shù): 27/108頁
文件大?。?/td> 0K
描述: IC FPGA SX 12K GATES 144-TQFP
標準包裝: 60
系列: SX-A
LAB/CLB數(shù): 768
輸入/輸出數(shù): 113
門數(shù): 12000
電源電壓: 2.25 V ~ 5.25 V
安裝類型: 表面貼裝
工作溫度: -40°C ~ 85°C
封裝/外殼: 144-LQFP
供應(yīng)商設(shè)備封裝: 144-TQFP(20x20)
SX-A Family FPGAs
v5.3
2-5
Figure 2-1 shows the 5 V PCI V/I curve and the minimum and maximum PCI drive characteristics of the SX-A family.
IOH = 11.9 * (VOUT – 5.25) * (VOUT + 2.45)
for VCCI > VOUT > 3.1V
EQ 2-1
IOL = 78.5 * VOUT * (4.4 – VOUT)
for 0V < VOUT < 0.71V
EQ 2-2
Figure 2-1 5 V PCI V/I Curve for SX-A Family
Voltage Out (V)
–200.0
–150.0
–100.0
–50.0
0.0
50.0
100.0
150.0
200.0
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
6
Current
(mA)
IOH
IOL
IOH MIN Spec
IOH MAX Spec
IOL MIN Spec
IOL MAX Spec
Table 2-9 DC Specifications (3.3 V PCI Operation)
Symbol
Parameter
Condition
Min.
Max.
Units
VCCA
Supply Voltage for Array
2.25
2.75
V
VCCI
Supply Voltage for I/Os
3.0
3.6
V
VIH
Input High Voltage
0.5VCCI
VCCI + 0.5
V
VIL
Input Low Voltage
–0.5
0.3VCCI
V
IIPU
Input Pull-up Voltage1
0.7VCCI
–V
IIL
Input Leakage Current2
0 < VIN < VCCI
–10
+10
μA
VOH
Output High Voltage
IOUT = –500 A
0.9VCCI
–V
VOL
Output Low Voltage
IOUT = 1,500 A
0.1VCCI
V
CIN
Input Pin Capacitance3
–10
pF
CCLK
CLK Pin Capacitance
5
12
pF
Notes:
1. This specification should be guaranteed by design. It is the minimum voltage to which pull-up resistors are calculated to pull a
floated network. Designers should ensure that the input buffer is conducting minimum current at this input voltage in applications
sensitive to static power utilization.
2. Input leakage currents include hi-Z output leakage for all bidirectional buffers with tristate outputs.
3. Absolute maximum pin capacitance for a PCI input is 10 pF (except for CLK).
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