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參數(shù)資料
| 型號： | A54SX32-2BG329I |
| 英文描述： | Field Programmable Gate Array (FPGA) |
| 中文描述： | 現(xiàn)場可編程門陣列（FPGA） |
| 文件頁數(shù)： | 26/36頁 |
| 文件大小： | 833K |
| 代理商： | A54SX32-2BG329I |
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54SX Family FPGAs RadTolerant and HiRel
26
v2.0
Pin Description
CLKA,
CLKB
These pins are clock inputs for clock distribution networks.
Input levels are compatible with standard TTL or LVTTL
specifications. The clock input is buffered prior to clocking
the R-cells. If not used, this pin must be set LOW or HIGH on
the board. It must not be left floating.
Clock A and B
GND
LOW supply voltage.
Ground
HCLK
Dedicated (Hard-wired)
Array Clock
This pin is the clock input for sequential modules. Input
levels are compatible with standard TTL or LVTTL
specifications. This input is directly wired to each R-cell and
offers clock speeds independent of the number of R-cells
being driven. If not used, this pin must be set LOW or HIGH
on the board. It must not be left floating.
I/O
The I/O pin functions as an input, output, tristate, or
bidirectional buffer. Based on certain configurations, input
and output levels are compatible with standard TTL or
LVTTL specifications. Unused I/O pins are automatically
tristated by the Designer Series software.
Input/Output
NC
This pin is not connected to circuitry within the device.
These pins can be driven to any voltage or can be left
floating with no effect on the operation of the device.
No Connection
PRA, I/O,
PRB, I/O
The Probe pin is used to output data from any user-defined
design node within the device. This independent diagnostic
pin can be used in conjunction with the other probe pin to
allow real-time diagnostic output of any signal path within
the device. The Probe pin can be used as a user-defined I/O
when verification has been completed. The pin
’
s probe
capabilities can be permanently disabled to protect
programmed design confidentiality.
Probe A/B
TCK, I/O
Test clock input for diagnostic probe and device
programming. In flexible mode, TCK becomes active when
the TMS pin is set LOW (see
Table 2 on page 9
). This pin
functions as an I/O when the JTAG state machine reaches
the
“
logic reset
“
state.
Test Clock (Input)
TDI, I/O
Serial input for boundary scan testing and diagnostic probe.
In flexible mode, TDI is active when the TMS pin is set LOW
(refer to
Table 2 on page 9
). This pin functions as an I/O
when the boundary scan state machine reaches the
“
logic
reset
”
state.
Test Data Input
TDO, I/O
Serial output for boundary scan testing. In flexible mode,
TDO is active when the TMS pin is set LOW (refer to
Table 2
on page 9
). This pin functions as an I/O when the boundary
scan state machine reaches the
“
logic reset
”
state.
Test Data Output
TMS
The TMS pin controls the use of the IEEE 1149.1 Boundary
Scan pins (TCK, TDI, TDO, TRST). In flexible mode when
the TMS pin is set LOW, the TCK, TDI, and TDO pins are
boundary scan pins (refer to
Table 2 on page 9
). Once the
boundary scan pins are in test mode, they will remain in that
mode until the internal boundary scan state machine
reaches the
“
logic reset
”
state. At this point, the boundary
scan pins will be released and will function as regular I/O
pins. The
“
logic reset
”
state is reached 5 TCK cycles after
the TMS pin is set HIGH. In dedicated test mode, TMS
functions as specified in the IEEE 1149.1 specifications.
Test Mode Select
TRST
The TRST pin functions as an active-low input to
asynchronously initialize or reset the boundary scan circuit.
The TRST pin is equipped with an internal pull-up resistor.
Boundary Scan Reset Pin
V
CCI
Supply voltage for I/Os. See
Table 1 on page 8
.
Supply Voltage
V
CCA
Supply voltage for Array. See
Table 1 on page 8
.
Supply Voltage
V
CCR
Supply voltage for input tolerance (required for internal
biasing). See
Table 1 on page 8
.
Supply Voltage
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| A54SX32-2BG329IX3 | 制造商:Microsemi Corporation 功能描述:FPGA SX Family 32K Gates 1800 Cells 320MHz 0.35um Technology 3.3V/5V 329-Pin BGA 制造商:Microsemi Corporation 功能描述:54SX 32K GATES 1800 MC 320MHZ IND CMOS 3.3/5V 329 BGA - Trays |
| A54SX32-2BGG329 | 功能描述:IC FPGA SX 48K GATES 329-BGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:SX 產(chǎn)品培訓模塊:Three Reasons to Use FPGA's in Industrial Designs Cyclone IV FPGA Family Overview 特色產(chǎn)品:Cyclone? IV FPGAs 標準包裝:60 系列:CYCLONE® IV GX LAB/CLB數(shù):9360 邏輯元件/單元數(shù):149760 RAM 位總計:6635520 輸入/輸出數(shù):270 門數(shù):- 電源電壓:1.16 V ~ 1.24 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:484-BGA 供應商設備封裝:484-FBGA（23x23） |
| A54SX32-2BGG329I | 功能描述:IC FPGA SX 48K GATES 329-BGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:SX 產(chǎn)品培訓模塊:Three Reasons to Use FPGA's in Industrial Designs Cyclone IV FPGA Family Overview 特色產(chǎn)品:Cyclone? IV FPGAs 標準包裝:60 系列:CYCLONE® IV GX LAB/CLB數(shù):9360 邏輯元件/單元數(shù):149760 RAM 位總計:6635520 輸入/輸出數(shù):270 門數(shù):- 電源電壓:1.16 V ~ 1.24 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:484-BGA 供應商設備封裝:484-FBGA（23x23） |
| A54SX322PQ208 | 制造商:ACTEL 功能描述:New |
| A54SX32-2PQ208 | 功能描述:IC FPGA SX 48K GATES 208-PQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:SX 產(chǎn)品培訓模塊:Three Reasons to Use FPGA's in Industrial Designs Cyclone IV FPGA Family Overview 特色產(chǎn)品:Cyclone? IV FPGAs 標準包裝:60 系列:CYCLONE® IV GX LAB/CLB數(shù):9360 邏輯元件/單元數(shù):149760 RAM 位總計:6635520 輸入/輸出數(shù):270 門數(shù):- 電源電壓:1.16 V ~ 1.24 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:484-BGA 供應商設備封裝:484-FBGA（23x23） |
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