參數(shù)資料
型號(hào)： A54SX32A-1CQG256C
元件分類： FPGA
英文描述： FPGA, 2880 CLBS, 32000 GATES, 241 MHz, CQFP256
封裝： CERAMIC, QFP-256
文件頁(yè)數(shù)： 14/40頁(yè)
文件大?。?/td> 738K
代理商： A54SX32A-1CQG256C
21
Hi R e l S X -A F a m i l y F P G A s
Ce l l Ti m i ng Cha r act e r i s t i cs
T i m i n g Ch ar ac t e r i st i c s
Timing characteristics for SX-A devices fall into three
categories:
family-dependent,
device-dependent,
and
design-dependent. The input and output buffer characteristics
are common to all SX-A family members. Internal routing
delays are device dependent. Design dependency means actual
delays are not determined until after placement and routing of
the user’s design are complete. Delay values may then be
determined by using the DirectTime Analyzer utility or
performing simulation with postlayout delays.
Cr i t i c al Net s and T y pi cal Ne ts
Propagation delays are expressed only for typical nets,
which are used for initial design performance evaluation.
Critical net delays can then be applied to the most timing
critical paths. Critical nets are determined by net property
assignment prior to placement and routing. Up to
six percent of the nets in a design may be designated as
critical, while 90 percent of the nets in a design are typical.
Long T r acks
Some nets in the design use long tracks. Long tracks are
special routing resources that span multiple rows, columns,
or modules.
Long tracks employ three to five antifuse
connections. This increases capacitance and resistance,
resulting in longer net delays for macros connected to long
tracks. Typically, up to six percent of nets in a fully utilized
device
require
long
tracks.
Long
tracks
contribute
approximately 4 ns to 8.4 ns delay. This additional delay is
represented statistically in higher fanout (FO=24) routing
delays in the Timing Characteristics tables starting on
Ti mi n g D e ra ti n g
SX-A devices are manufactured with a CMOS process.
Therefore,
device
performance
varies
according
to
temperature, voltage, and process changes. Minimum timing
parameters reflect maximum operating voltage, minimum
operating temperature, and best-case processing. Maximum
timing parameters reflect minimum operating voltage,
maximum operating temperature, and worst-case processing.
T e m p e r at ur e a n d V o l t ag e De ra t i ng F a c t o r s
( N o r ma l i ze d to Wo rs t- C a s e C o mme rc i a l , T J = 70°C, V CCA = 2.3 V)
(Positive edge triggered)
D
CLK
CLR
Q
D
CLK
Q
CLR
tHPWH,
tWASYN
tHD
tSUD
tHP
tHPWL,
tRCO
tCLR
tRPWL
tRPWH
PRESET
tPRESET
PRESET
F l ip - F lo p s
VCCA
Junction Temperature (TJ)
–55
–40
0
25
70
85
125
2.3
0.75
.079
0.88
0.89
1.00
1.04
1.16
2.5
0.70
0.74
0.82
0.83
0.93
0.97
1.08
2.7
0.66
0.69
0.79
0.88
0.92
1.02
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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