參數(shù)資料
型號(hào)： A54SX32A-1CQG256C
元件分類(lèi)： FPGA
英文描述： FPGA, 2880 CLBS, 32000 GATES, 241 MHz, CQFP256
封裝： CERAMIC, QFP-256
文件頁(yè)數(shù)： 24/40頁(yè)
文件大?。?/td> 738K
代理商： A54SX32A-1CQG256C
30
Pi n D e s c r i pt i o n
CLKA/B
Clock A and B
These pins are 3.3V/5.0V PCI/TTL clock inputs for clock
distribution networks. The clock input is buffered prior to
clocking the R-cells. If not used, this pin must be set LOW or
HIGH on the board. It must not be left floating. (For
A54SX72A, these clocks can be configured as bidirectional.)
QCLKA/B/C/D Quadrant Cl ock A, B, C, a nd D
These four pins are the quadrant clock inputs. They are
3.3V/5.0V PCI/TTL clock input for clock distribution
networks. Each of these clock inputs can drive up to a
quarter of the chip, or they can be grouped together to drive
multiple quadrants. The clock input is buffered prior to
clocking the R-cells. If not used, this pin must be set LOW or
HIGH on the board. It must not be left floating. (These
quadrant clocks are only for A54SX72A).
GND
Ground
LOW supply voltage.
HCLK
Dedicated (Hardwired)
Array Clock
This pin is the 3.3V/5.0V PCI/TTL clock input for sequential
modules. This input is directly wired to each R-cell and
offers clock speeds independent of the number of R-cells
being driven. If not used, this pin must be set LOW or HIGH
on the board. It must not be left floating.
I/O
Input/Output
The I/O pin functions as an input, output, tristate, or
bidirectional buffer. Based on certain configurations, input
and output levels are compatible with standard TTL, LVTTL,
3.3V PCI, or 5.0V PCI specifications. Unused I/O pins are
automatically tristated by the Designer Series software.
NC
No Connection
This pin is not connected to circuitry within the device.
PR A, I/O
Probe A
The Probe A pin is used to output data from any
user-defined
design
node
within
the
device.
This
independent diagnostic pin can be used in conjunction with
the Probe B pin to allow real-time diagnostic output of any
signal path within the device. The Probe A pin can be used
as a user-defined I/O when verification has been completed.
The pin’s probe capabilities can be permanently disabled to
protect programmed design confidentiality.
PR B, I/O
Probe B
The Probe B pin is used to output data from any node within
the device. This diagnostic pin can be used in conjunction
with the Probe A pin to allow real-time diagnostic output of
any signal path within the device. The Probe B pin can be
used as a user-defined I/O when verification has been
completed. The pin’s probe capabilities can be permanently
disabled to protect programmed design confidentiality.
TCK
Test Clock
Test
clock
input
for
diagnostic
probe
and
device
programming. In flexible mode, TCK becomes active when
the TMS pin is set LOW (refer to Table 2 on page 10). This
pin functions as an I/O when the boundary scan state
machine reaches the “l(fā)ogic reset” state.
TDI
Test Data Input
Serial input for boundary scan testing and diagnostic probe.
In flexible mode, TDI is active when the TMS pin is set LOW
(refer to Table 2 on page 10). This pin functions as an I/O
when the boundary scan state machine reaches the “l(fā)ogic
reset” state.
TDO
Test Data Output
Serial output for boundary scan testing. In flexible mode,
TDO is active when the TMS pin is set LOW (refer to Table 2
on page 10). This pin functions as an I/O when the boundary
scan state machine reaches the “l(fā)ogic reset” state.
TMS
Test Mode Select
The TMS pin controls the use of the IEEE 1149.1 Boundary
Scan pins (TCK, TDI, TDO). In flexible mode when the TMS
pin is set LOW, the TCK, TDI, and TDO pins are boundary
scan pins (refer to Table 2 on page 10). Once the boundary
scan pins are in test mode, they will remain in that mode
until the internal boundary scan state machine reaches the
“l(fā)ogic reset” state. At this point, the boundary scan pins will
be released and will function as regular I/O pins. The “l(fā)ogic
reset” state is reached 5 TCK cycles after the TMS pin is set
HIGH. In dedicated test mode, TMS functions as specified in
the IEEE 1149.1 Specifications.
TRST
Boundary Scan (JTAG) Reset Pin
Once configured as the Boundary Scan Reset pin, the TRST
pin functions as an active low input to asynchronously
initialize or reset the boundary scan circuit. The TRST is
equipped with an internal pull-up resistor. This pin
functions as an I/O when “Reserve JTAG Reset Pin” is not
selected in Designer.
V CCI
Supply Voltage
Supply voltage for I/Os. See Table 1 on page 9.
V CCA
Supply Voltage
Supply voltage for Array. See Table 1 on page 9.
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