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參數資料
| 型號： | A54SX32A-1CQG256C |
| 元件分類： | FPGA |
| 英文描述： | FPGA, 2880 CLBS, 32000 GATES, 241 MHz, CQFP256 |
| 封裝： | CERAMIC, QFP-256 |
| 文件頁數： | 40/40頁 |
| 文件大?。?/td> | 738K |
| 代理商： | A54SX32A-1CQG256C |
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9
Hi R e l S X -A F a m i l y F P G A s
FastConnect enables horizontal routing between any two
logic modules within a given SuperCluster and vertical
routing with the SuperCluster immediately below it. Only
one programmable connection is used in a FastConnect
path, delivering maximum pin-to-pin propagation of 0.2 ns.
In addition to DirectConnect and FastConnect, the
architecture makes use of two globally oriented routing
resources known as segmented routing and high-drive
routing. Actel’s segmented routing structure provides a
variety of track lengths for extremely fast routing between
SuperClusters. The exact combination of track lengths and
antifuses within each path is chosen by the 100 percent
automatic place-and-route software to minimize signal
propagation delays.
Actel’s high-drive routing structure provides three clock
networks. The first clock, called HCLK, is hardwired from
the HCLK buffer to the clock select MUX in each R-cell. This
provides a fast propagation path for the clock signal,
enabling the 5.3 ns clock-to-out (pin-to-pin) performance of
the SX-A devices. The hardwired clock is tuned to provide
clock skew as low as 0.29 ns. The remaining two clocks
(CLKA, CLKB) are global clocks that can be sourced from
external pins or from internal logic signals within the SX-A
device.
In addition, the A54SX72A device provides four quadrant
clocks (QCLKA, QCLKB, QCLKC, QCLKD), which can be
sourced from external pins or from internal logic signals
within the device. Each of these clocks can individually
drive up to a quarter of the chip, or they can be grouped
together to drive multiple quadrants.
O t he r A r c h i t ec tu ral Fe atu r e s
T echno l o g y
Actel’s SX-A family is implemented on a high-voltage
twin-well CMOS process using 0.25
design rules (moving
quickly to 0.22
). The metal-to-metal antifuse is made up of
a combination of amorphous silicon and dielectric material
with barrier metals and has a programmed (“on” state)
resistance of 25 ohms with capacitance of 1.0 fF for low
signal impedance.
P e rf orm a nce
The combination of architectural features described above
enables SX-A devices to operate with internal clock
frequencies exceeding 284 MHz, enabling very fast
execution of even complex logic functions. Thus, the SX-A
family is an optimal platform upon which to integrate the
functionality previously contained in multiple CPLDs. In
addition, designs that previously would have required a gate
array to meet performance goals can now be integrated into
an SX-A device with dramatic improvements in cost and
time to market. Using timing-driven place-and-route tools,
designers
can
achieve
highly
deterministic
device
performance. With SX-A devices, designers do not need to
use complicated performance-enhancing design techniques
such as the use of redundant logic to reduce fanout on
critical nets or the instantiation of macros in HDL code to
achieve high performance.
I/ O M odul es
Each I/O on an SX-A device can be configured as an input,
an output, a tristate output, or a bidirectional pin. Even
without the inclusion of dedicated I/O registers, these I/Os,
in
combination
with
array
registers,
can
achieve
clock-to-out (pad-to-pad) timing as fast as 5.3 ns. I/O cells
that have embedded latches and flip-flops require
instantiation in HDL code; this is a design complication not
encountered in SX-A FPGAs. Fast pin-to-pin timing ensures
that the device will have little trouble interfacing with any
other device in the system, which in turn enables parallel
design of system components and reduces overall design
time.
Hot S w a ppi n g
SX-A I/Os are specifically designed to be programmed to be
hot swappable. During power-up/down (or partial up/down),
all I/Os are tristated. VCCA and VCCI do not have to be stable
during power up/down and they do not require a specific
power up or power down sequence in order to avoid damage
to the SX-A devices. After the SX-A device is plugged into an
electrically active system, the device will not degrade the
reliability of or cause damage to the host system. The
devices’ output pins are driven to a high impedance state
until normal chip operating conditions are reached.
P o wer Requ i r em ent s
The SX-A family supports 2.5V/3.3V/5.0V mixed voltage
operation and is designed to tolerate 5.0V inputs in each
case (Table 1). Power consumption is extremely low due to
the very short distances signals are required to travel to
complete a circuit. Power requirements are further reduced
because of the small number of low resistance antifuses in
the path. The antifuse architecture does not require active
circuitry to hold a charge (as do SRAM or EPROM), making
it the lowest-power architecture FPGA available today.
Table 1 Supply Voltages
VCCA
VCCI
Maximum
Input
Tolerance
Maximum
Output
Drive
A54SX32A
A54SX72A
2.5V
5.0V
2.5V
3.3V
5.0V
3.3V
2.5V
5.0V
相關PDF資料 |
PDF描述 |
|---|---|
| A54SX32A-CQ208C | FPGA, 2880 CLBS, 32000 GATES, 206 MHz, CQFP208 |
| A54SX32A-CQ256C | FPGA, 2880 CLBS, 32000 GATES, 206 MHz, CQFP256 |
| A54SX32A-CQG208C | FPGA, 2880 CLBS, 32000 GATES, 206 MHz, CQFP208 |
| A54SX32A-CQG256C | FPGA, 2880 CLBS, 32000 GATES, 206 MHz, CQFP256 |
| A54SX72A-FG256AX79 | FPGA, 4024 CLBS, 72000 GATES, PBGA256 |
相關代理商/技術參數 |
參數描述 |
|---|---|
| A54SX32A-1FG144 | 功能描述:IC FPGA SX 48K GATES 144-FBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:SX-A 標準包裝:40 系列:SX-A LAB/CLB數:6036 邏輯元件/單元數:- RAM 位總計:- 輸入/輸出數:360 門數:108000 電源電壓:2.25 V ~ 5.25 V 安裝類型:表面貼裝 工作溫度:0°C ~ 70°C 封裝/外殼:484-BGA 供應商設備封裝:484-FPBGA（27X27） |
| A54SX32A-1FG144I | 功能描述:IC FPGA SX 48K GATES 144-FBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:SX-A 標準包裝:40 系列:SX-A LAB/CLB數:6036 邏輯元件/單元數:- RAM 位總計:- 輸入/輸出數:360 門數:108000 電源電壓:2.25 V ~ 5.25 V 安裝類型:表面貼裝 工作溫度:0°C ~ 70°C 封裝/外殼:484-BGA 供應商設備封裝:484-FPBGA（27X27） |
| A54SX32A-1FG144M | 制造商:Microsemi Corporation 功能描述:FPGA SX-A 32K GATES 1800 CELLS 278MHZ 0.25UM/0.22UM 2.5V 144 - Trays 制造商:Microsemi Corporation 功能描述:IC FPGA 111 I/O 144FBGA |
| A54SX32A-1FG256 | 功能描述:IC FPGA SX 48K GATES 256-FBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:SX-A 標準包裝:40 系列:SX-A LAB/CLB數:6036 邏輯元件/單元數:- RAM 位總計:- 輸入/輸出數:360 門數:108000 電源電壓:2.25 V ~ 5.25 V 安裝類型:表面貼裝 工作溫度:0°C ~ 70°C 封裝/外殼:484-BGA 供應商設備封裝:484-FPBGA（27X27） |
| A54SX32A-1FG256I | 功能描述:IC FPGA SX 48K GATES 256-FBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:SX-A 標準包裝:40 系列:SX-A LAB/CLB數:6036 邏輯元件/單元數:- RAM 位總計:- 輸入/輸出數:360 門數:108000 電源電壓:2.25 V ~ 5.25 V 安裝類型:表面貼裝 工作溫度:0°C ~ 70°C 封裝/外殼:484-BGA 供應商設備封裝:484-FPBGA（27X27） |
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