參數(shù)資料
型號(hào)： A54SX32A-FG256
廠商： Microsemi SoC
文件頁(yè)數(shù)： 12/108頁(yè)
文件大?。?/td> 0K
描述： IC FPGA SX 48K GATES 256-FBGA
標(biāo)準(zhǔn)包裝： 90
系列： SX-A
LAB/CLB數(shù)： 2880
輸入/輸出數(shù)： 203
門數(shù)： 48000
電源電壓： 2.25 V ~ 5.25 V
安裝類型： 表面貼裝
工作溫度： 0°C ~ 70°C
封裝/外殼： 256-LBGA
供應(yīng)商設(shè)備封裝： 256-FPBGA（17x17）
SX-A Family FPGAs
v5.3
1-7
Other Architectural Features
Technology
The Actel SX-A family is implemented on a high-voltage,
twin-well CMOS process using 0.22
μ /0.25 μ design
rules. The metal-to-metal antifuse is comprised of a
combination of amorphous silicon and dielectric material
with barrier metals and has a programmed ('on' state)
resistance of 25
Ω with capacitance of 1.0 fF for low
signal impedance.
Performance
The unique architectural features of the SX-A family
enable the devices to operate with internal clock
frequencies of 350 MHz, causing very fast execution of
even complex logic functions. The SX-A family is an
optimal
platform
upon
which
to
integrate
the
functionality previously contained in multiple complex
programmable logic devices (CPLDs). In addition, designs
that previously would have required a gate array to meet
performance goals can be integrated into an SX-A device
with dramatic improvements in cost and time-to-market.
Using timing-driven place-and-route tools, designers can
achieve highly deterministic device performance.
User Security
Reverse engineering is virtually impossible in SX-A
devices because it is extremely difficult to distinguish
between programmed and unprogrammed antifuses. In
addition, since SX-A is a nonvolatile, single-chip solution,
there is no configuration bitstream to intercept at device
power-up.
The Actel FuseLock advantage ensures that unauthorized
users will not be able to read back the contents of an
Actel antifuse FPGA. In addition to the inherent
strengths of the architecture, special security fuses that
prevent internal probing and overwriting are hidden
throughout the fabric of the device. They are located
where they cannot be accessed or bypassed without
destroying access to the rest of the device, making both
invasive and more-subtle noninvasive attacks ineffective
against Actel antifuse FPGAs.
Look for this symbol to ensure your valuable IP is secure
For more information, refer to Actel’s Implementation of
I/O Modules
For a simplified I/O schematic, refer to Figure 1 in the
Each user I/O on an SX-A device can be configured as an
input, an output, a tristate output, or a bidirectional pin.
Mixed I/O standards can be set for individual pins,
though this is only allowed with the same voltage as the
input. These I/Os, combined with array registers, can
achieve clock-to-output-pad timing as fast as 3.8 ns, even
without the dedicated I/O registers. In most FPGAs, I/O
cells
that
have
embedded
latches
and
flip-flops,
requiring instantiation in HDL code; this is a design
complication not encountered in SX-A FPGAs. Fast pin-
to-pin timing ensures that the device is able to interface
with any other device in the system, which in turn
enables parallel design of system components and
reduces overall design time. All unused I/Os are
configured as tristate outputs by the Actel Designer
software, for maximum flexibility when designing new
boards or migrating existing designs.
SX-A I/Os should be driven by high-speed push-pull
devices with a low-resistance pull-up device when being
configured as tristate output buffers. If the I/O is driven
by a voltage level greater than VCCI and a fast push-pull
device is NOT used, the high-resistance pull-up of the
driver and the internal circuitry of the SX-A I/O may
create a voltage divider. This voltage divider could pull
the input voltage below specification for some devices
connected to the driver. A logic '1' may not be correctly
presented in this case. For example, if an open drain
driver is used with a pull-up resistor to 5 V to provide the
logic '1' input, and VCCI is set to 3.3 V on the SX-A device,
the input signal may be pulled down by the SX-A input.
Each I/O module has an available power-up resistor of
approximately 50 k
Ω that can configure the I/O in a
known state during power-up. For nominal pull-up and
pull-down resistor values, refer to Table 1-4 on page 1-8
of the application note Actel eX, SX-A, and RTSX-S I/Os.
Just slightly before VCCA reaches 2.5 V, the resistors are
disabled, so the I/Os will be controlled by user logic. See
more information concerning available I/O features.
Figure 1-11 FuseLock
e
u
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A54SX32A-FG256A 功能描述:IC FPGA SX 48K GATES 256-FBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門陣列） 系列:SX-A 標(biāo)準(zhǔn)包裝:40 系列:SX-A LAB/CLB數(shù):6036 邏輯元件/單元數(shù):- RAM 位總計(jì):- 輸入/輸出數(shù):360 門數(shù):108000 電源電壓:2.25 V ~ 5.25 V 安裝類型:表面貼裝 工作溫度:0°C ~ 70°C 封裝/外殼:484-BGA 供應(yīng)商設(shè)備封裝:484-FPBGA（27X27）
A54SX32A-FG256I 功能描述:IC FPGA SX 48K GATES 256-FBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門陣列） 系列:SX-A 標(biāo)準(zhǔn)包裝:40 系列:SX-A LAB/CLB數(shù):6036 邏輯元件/單元數(shù):- RAM 位總計(jì):- 輸入/輸出數(shù):360 門數(shù):108000 電源電壓:2.25 V ~ 5.25 V 安裝類型:表面貼裝 工作溫度:0°C ~ 70°C 封裝/外殼:484-BGA 供應(yīng)商設(shè)備封裝:484-FPBGA（27X27）
A54SX32A-FG256M 制造商:Microsemi Corporation 功能描述:FPGA SX-A 32K GATES 1800 CELLS 238MHZ 0.25UM/0.22UM 2.5V 256 - Trays 制造商:Microsemi Corporation 功能描述:IC FPGA 48K GATES 256FBGA 制造商:Microsemi Corporation 功能描述:IC FPGA 203 I/O 256FBGA
A54SX32A-FG484 功能描述:IC FPGA SX 48K GATES 484-FBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門陣列） 系列:SX-A 標(biāo)準(zhǔn)包裝:40 系列:SX-A LAB/CLB數(shù):6036 邏輯元件/單元數(shù):- RAM 位總計(jì):- 輸入/輸出數(shù):360 門數(shù):108000 電源電壓:2.25 V ~ 5.25 V 安裝類型:表面貼裝 工作溫度:0°C ~ 70°C 封裝/外殼:484-BGA 供應(yīng)商設(shè)備封裝:484-FPBGA（27X27）
A54SX32A-FG484I 功能描述:IC FPGA SX 48K GATES 484-FBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門陣列） 系列:SX-A 產(chǎn)品培訓(xùn)模塊:Three Reasons to Use FPGA's in Industrial Designs Cyclone IV FPGA Family Overview 特色產(chǎn)品:Cyclone? IV FPGAs 標(biāo)準(zhǔn)包裝:60 系列:CYCLONE® IV GX LAB/CLB數(shù):9360 邏輯元件/單元數(shù):149760 RAM 位總計(jì):6635520 輸入/輸出數(shù):270 門數(shù):- 電源電壓:1.16 V ~ 1.24 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:484-BGA 供應(yīng)商設(shè)備封裝:484-FBGA（23x23）
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