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參數(shù)資料
| 型號： | a8237 |
| 廠商： | Altera Corporation |
| 英文描述： | programmable DMA Controller(可編程DMA控制器) |
| 中文描述： | 可編程DMA控制器（可編程DMA的控制器） |
| 文件頁數(shù)： | 14/22頁 |
| 文件大?。?/td> | 269K |
| 代理商： | A8237 |
18
Altera Corporation
a8237 Programmable DMA Controller Data Sheet
State Machine
The
a8237
state machine synchronously controls various functions and
can execute two types of DMA transfers. The memory to/from I/O
transfer executes a simultaneous read and write operation, which requires
a total of four states. The memory-to-memory transfer must perform the
read and write operation separately, which requires a total of eight states
(i.e., four states to read a memory location and store the data value in the
temporary register, and another four to write the data value to a new
memory location). The state machine loops through these states until the
word count decrements to zero or until the transfer is externally aborted.
Upon reset, the state machine enters an SI state. In the SI state, the internal
registers can be programmed to the appropriate configuration. After
programming, the
a8237
continuously samples any unmasked DMA
request (
dreq
) inputs. If a valid
dreq
is detected, the state machine
transitions into the acquire bus state. See
Figure 3 on page 22
.
In the S0 state, the
hrq
output is asserted, and the state machine waits for
the microprocessor to assert
hlda
. When the
hlda
input is asserted, the
a8237
controls the microprocessor via the 8-bit data bus, allowing DMA
transfers to begin.
I
The S1 state is the first state of a DMA transfer, where the
aen
and
adstb
signals are asserted. The most significant byte of the address
appears on the
dbout[7..0]
bus, and the least significant byte of the
address appears on the
aout[7..0]
bus.
I
The S2 state is the second state, where
adstb
is deasserted, latching
the most significant byte of the address from
dbout[7..0]
into the
external latch.
I
The S3 state is the third state, where
niorout
or
nmemr
is asserted,
depending on the direction of the DMA transfer.
I
The S4 state is the fourth state, where
niowout
or
nmemw
is asserted.
If the end of the DMA cycle has not been reached, the state machine
loops to the S2 state for the next transfer. If the most significant byte
of the address does not change in subsequent cycles of the DMA
transfer, then the S4 state transitions directly to the S2 state (i.e., the
S1 state is skipped), which effectively suppresses
adstb
generation
and speeds up block transfers.
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|---|---|
| A82370-16 | 制造商:Rochester Electronics LLC 功能描述: |
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| A82380-20 | 制造商:Rochester Electronics LLC 功能描述: |
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| A82385-16 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Cache Controller |
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