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參數(shù)資料
| 型號(hào)： | a8237 |
| 廠商： | Altera Corporation |
| 英文描述： | programmable DMA Controller(可編程DMA控制器) |
| 中文描述： | 可編程DMA控制器（可編程DMA的控制器） |
| 文件頁數(shù)： | 5/22頁 |
| 文件大小： | 269K |
| 代理商： | A8237 |
Altera Corporation
9
a8237 Programmable DMA Controller Data Sheet
The microprocessor can program the
a8237
when the
ncs
input and the
ain[3..0]
bus are asserted. When
niowin
and
ain[3..0]
are asserted,
the microprocessor writes data to internal registers via the
dbin[7..0]
bus. When
niorin
and
ain[3..0]
are asserted, the microprocessor reads
data from internal registers via the
dbout[7..0]
bus. See
“Host Processor
Write Timing”
and
“Host Processor Read Timing”
in
Figure 3.
The byte pointer bit must be toggled to the correct value before operating
on the DMA address register and word count register. The set byte
pointer and clear mode register counter commands can change the
contents of registers, effectively acting as write commands.
Register Address Map
Table 2
shows the register address map for the
a8237
.
Notes:
(1)
If the byte pointer is set to 0, the byte pointer flag selects the least significant byte.
If the byte pointer is set to 1, the byte pointer flag selects the most significant byte.
The byte pointer flag is a single-bit internal register that selects either the least significant or most significant byte
of the 16-bit registers in the
a8237
, allowing the microprocessor to write and read via the 8-bit data bus. See
“Clear
Byte Pointer Command”
and
“Set Byte Pointer Command” on page 17
for more information.
The X indicates “don’t care.”
(2)
Table 2. Register Address Map
ain3 ain2 ain1 ain0
Channel
Write
(1)
,
(2)
Read
(1)
,
(2)
0
0
0
0
0
Base and current DMA address register
Current DMA address register
0
0
0
1
Base and current DMA word count register
Current DMA word count register
0
0
1
0
1
Base and current DMA address register
Current DMA address register
0
0
1
1
Base and current DMA word count register
Current DMA word count register
0
1
0
0
2
Base and current DMA address register
Current DMA address register
0
1
0
1
Base and current DMA word count register
0
1
1
0
3
Base and current DMA address register
Current DMA address register
0
1
1
1
Base and current DMA word count register
Current DMA word count register
1
0
0
0
X
X
X
X
X
X
X
X
Command register
Status register
1
0
0
1
Single request bit command
Request register
1
0
1
0
Single mask bit command
Command register
1
0
1
1
Mode register
Mode register
1
1
0
0
Clear byte pointer command
Set byte pointer command
1
1
0
1
Master clear command
Temporary register
1
1
1
0
Clear mask register command
Clear mode register counter
1
1
1
1
Mask register
Mask register
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|---|---|
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