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參數(shù)資料
| 型號(hào)： | A8237 |
| 廠商： | Altera Corporation |
| 英文描述： | PROGRAMMABLE DMA CONTROLLER |
| 中文描述： | 可編程DMA控制器 |
| 文件頁數(shù)： | 10/22頁 |
| 文件大小： | 269K |
| 代理商： | A8237 |
14
Altera Corporation
a8237 Programmable DMA Controller Data Sheet
Mask Register
The 4-bit mask register can be set to disable an incoming DMA request,
and contains the mask flags for the
dreq
inputs of each channel. The
microprocessor can read or write to the mask register via the 8-bit data
bus. Also, the microprocessor can write individual bits of the mask
register with the single mask bit command. The
reset
input or a master
clear command sets all bits in the mask register. See
Table 6
.
Note:
(1)
The X indicates “don’t care.”
Status Register
The 8-bit status register contains the status flags of the four DMA
channels. Each DMA channel has a terminal count flag and a request flag.
The terminal count flag indicates that a DMA cycle is complete or has been
terminated by the
neopin
signal since the last read of the status register.
The request flag indicates the
dreq
input of a channel is asserted
regardless of the state of the associated mask bit. The status register is
reset by the
reset
input or the master clear command. The terminal count
flags are reset on each read of the status register. See
Table 7
.
Table 6. Mask Register Format
Bit
Description
0
0 = Channel 0 unmasked
1 = Channel 0 masked
0 = Channel 1 unmasked
1 = Channel 1 masked
0 = Channel 2 unmasked
1 = Channel 2 masked
0 = Channel 3 unmasked
1 = Channel 3 masked
XXXX during write,
Note (1)
1111 during read
1
2
3
7..4
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