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參數(shù)資料
| 型號： | A8237 |
| 廠商： | Altera Corporation |
| 英文描述： | PROGRAMMABLE DMA CONTROLLER |
| 中文描述： | 可編程DMA控制器 |
| 文件頁數(shù)： | 7/22頁 |
| 文件大?。?/td> | 269K |
| 代理商： | A8237 |
Altera Corporation
11
a8237 Programmable DMA Controller Data Sheet
Base Word Count Register
Each of the four DMA channels has a base word count register, which is a
16-bit register containing the beginning word count for DMA transfers. If
auto-initialization is enabled, the
a8237
loads the base word count value
into the current word count register at the conclusion of a DMA cycle. The
microprocessor writes to the base word count register in two parts via
dbin[7..0]
, and simultaneously loads the current word count register.
The byte pointer flag chooses the least significant or most significant byte.
The microprocessor cannot read the base word count register.
Current Word Count Register
Each of the four DMA channels has a current word count register, which
is a 16-bit register containing the working word count value for DMA
transfers. The microprocessor loads the current word count value
simultaneously with the base word count register via
dbin[7..0]
. If
auto-initialization is enabled, the
a8237
reloads the base word count
value at the conclusion of a DMA cycle. The microprocessor reads or
writes to the current word count register in two parts via the 8-bit data
bus. The byte pointer flag chooses the least significant or most significant
byte. After each DMA transfer, the current word count value is updated
with the decremented value from the temporary word count register. A
terminal count flag is generated when the count rolls over from zero to
hexadecimal
FFFF
. The number of DMA transfers is one more than the
value written to the current word count register. For example, if a 16-word
transfer is desired, the word count should be hexadecimal
000F
.
Command Register
The command register configures the operation of the
a8237
, such as
dreq
and
dack
polarity, request priority, function enables/disables, and
transfer timing. The microprocessor reads from or writes to the command
register via the 8-bit data bus. The
reset
input or a master clear command
clears the command register. See
Table 3
.
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