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參數(shù)資料
| 型號： | A8255 |
| 廠商： | Altera Corporation |
| 英文描述： | PROGRAMMABLE PERIPHERAL INTERFACE ADAPTER |
| 中文描述： | 可編程外圍接口適配器 |
| 文件頁數(shù)： | 12/13頁 |
| 文件大?。?/td> | 250K |
| 代理商： | A8255 |
56
Altera Corporation
a8255 Programmable Peripheral Interface Adapter Data Sheet
Figure 4. a8255 Mode 2 Functional Timng Waveforms
Variations &
Clarifications
The following characteristics distinguish the Altera
a8255
from the
Intel 8255A and Harris 82C55A devices:
I
To allow synchronous design, a
clk
input was added as a system
clock to the
a8255
. This capability requires that all strobes (
nrd
,
nwr
,
nstb
, and
nack
) have a minimum pulse width of one
clk
cycle.
In the
a8255
, the
reset
input resets the port A, B, and C registers.
In the Intel 8255A and Harris 82C55A devices, the port A, B, and C
registers are unaffected by the
reset
input.
The bidirectional buses in the Intel 8255A and Harris 82C55A devices
(
d
,
pa
,
pb
, and
pc
) are split into input, output, and enable signals in
the Altera
a8255
.
The
a8255
has no “bus hold” passive pull-ups on port signals.
Because the port I/O signal is usually tied to the I/O of the Altera
device, pull-ups or pull-downs can be added.
In the
a8255
, the control register can be read. The control register can
be read on the Harris 82C55A device, but the Intel 8255A device does
not have this capability.
In the
a8255
, the
reset
signal initializes the control register such
that all ports are set to mode 0 inputs. Reading the control register
after initialization will return the value of 9B in hexadecimal.
After initialization in mode 1, the pertinent control signals in the
port C register should be configured via the port C bit set/reset
commands.
In mode 2, every read or write of port A resets the
intra
interrupt
signal.
The Intel and Harris data sheets state that output registers and status
flipflops should be reset in the event of a mode change. This feature
was not included in the
a8255
.
I
I
I
I
I
I
I
I
Mode 2: Bidirectional Bus
Data from a8255
Data from Peripheral
nwr
nobf
intr
nack
nstb
ibf
Peripheral
Bus
nrd
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